Posted on 01 August 2019

2nd Generation Si and SiC SGTOs for Extreme Pulse Power and Sub-Microsecond Switching

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Through a series of ARL Cooperative Agreements, Silicon Power has been able to optimize Silicon and SiC Super GTOs (SGTOs) for extreme pulse power, operating in excess of 10kA/cm2, about a 10-fold higher density than the traditional thyristor. Moreover, SGTO active turn-off also provides the opportunity for supporting recovery voltage times (tq) of 10μs or less at high dV/dt.

V. Temple, J. Waldron, F. Holroyd, S. Almarayati and J. Azotea, Silicon Power Corporation, 958 Main St, Suite A, Clifton Park, NY 12065, USA

This article will detail both Silicon and SiC devices and modules operating at these power densities and some of the modeling that supported 2nd generation SGTO success.


Silicon Power’s SGTO is an IC foundry-fabricated GTO. Despite designing the SGTO to several generation old design rules (ensuring high yields) the cell structure is 3,000 times denser than legacy GTO designs. The planar design of the junction termination extension (JTE) allows replacing the deep diffusion junction with shallow ion implanted emitter and upper base. The thinner upper base lowers the series resistance of the device, while simultaneously reducing the requisite charge to be removed during turn-off, see Figure 1.

Upper: SGTO cell density compared to legacy GTO cell density. Lower: Deep diffusion legacy technology compared to planar IC foundry-fabricated SGTO

The increased cell density improves current uniformity. Combining these benefits yields a greatly reduced forward drop, a 3x reduction in turnoff losses and 100x improvement of turn-on losses.

Enabling a cell density of 160,000/cm2 is Silicon Power’s proprietary ThinPak lid [1]. ThinPak replaces wire bonds to intimately contact the highly interdigitated fingers with very low parasitic resistance and inductance. Further benefits of ThinPak include: orders of magnitude improvement in thermal cycling over wire bond [2], a robust known good die (KGD) platform to increase module yields and large top side metal patterns for electrode attachment, as shown in Figure 2.

A) 3.3cm2 SGTO B) 2cm2 ThinPak C) Assembled SGTO ThinPak D) X-Ray and electrically tested ThinPak E) KGD ThinPak passivated for strike and creep

Simulations of Gen2 Technology

First generation SGTOs achieved current densities over 6kA/cm2, but suffered from higher than anticipated losses under very high dI/dt conditions and lower than expected I2t capability (10,000A2s). To improve upon first generation technology a study was done to investigate: the impact of percentage of emitter area, current distributions within a cell and current distribution across several cells with a common metal emitter electrode. The impact of percentage of emitter area on I2t capability was calculated using a lumped charge model to simulate turn-on and conduction losses allowing a maximum temperature rise of 400C, see Figure 3.

I2t capability as a function of percentage of emitter area and pulse width

The minimum pulse width calculated in Figure 3 can be reduced further by increasing the gate current triggering the device. For each factor of e increase in gate current the curve can be shifted to the left by one transit time (55ns for a 6kV Si SGTO).

With the impact of emitter area understood, the current distribution across the cell with ideal ohmic contacts was simulated. Current crowding at the edge of the gate electrode is inevitable, but is mitigated by increasing the emitter area. Figure 4 demonstrates this effect as a function of total device current.

Vertical current flow lines for a 10mm SiC SGTO carrying 20A (left) and 9kA (right)

Exacerbating this affect is the finite resistance of the emitter electrodes connecting several cells. As the current flows laterally through the emitter/electrode a resistive voltage drop develops. This voltage drop debiases the gate and reduces injection into the lower base, further degrading performance. While ThinPak greatly reduces the lateral distance current must travel compared to wire bonds, the high cell density mandates that some lateral current must flow through the emitter electrode before reaching the ThinPak lid.

To quantitatively study the debiasing due to lateral current flow, several emitter electrodes were placed on the emitter and connected in series with resistors in the mixed mode simulation. This enabled finite resistance to be added between the electrodes, simulating the resistance of the 4mm thick gold electrodes used in fabrication. As Figure 5 shows, the debiasing becomes severe enough to completely eliminate injection at points as close as 120μm from the ThinPak electrode connection. The current flow lines as a function of device current can be found in Appendix A.

Cross-section of several cells sharing one electrode

Figure 5 also serves to demonstrate the upper bound for spacing the electrodes in Gen2 designs. Interestingly, because SiC needs one tenth the thickness of epi to support the same voltage as Si, this nonuniform current flow is still evident at the back of the device. Figure 6, Upper shows how poor the current balance becomes without careful design. Local temperature rise within the device is proportional to the power density; Figure 6, Lower demonstrates the impact non-uniform current distributions have on temperature gradients, reducing the number of pulses before a failure occurs.

Current distribution of 9kA Pulse through a 10mm device

Gen2 Si and SiC SGTO designs were carefully laid out to mitigate current non-uniformities. Complimentary devices to Gen2-on, the Gen2-off were also studied. For Gen2-off, the gate area is increased relative to emitter area. The larger gate area reduces current crowding in the upper base during turn-off, when the anode current must be extracted from the gate terminal. The reduction of this current crowding mitigates rebiasing of the upper base-emitter junction which results in failed turn-off.

Experimental Results

The first Gen2-on devices were designed with the same active area as our Gen1 device, making direct comparisons between the two technologies completely transparent.

The Gen2-on device increases the Gen1 emitter area by a factor of 2.7, roughly the same ratio of resistance between the two technologies. However, because the current is distributed more uniformly, and therefore the temperature excursions are less severe, the I2t capability for the Gen2-on device is more than doubled (22.6kA2s), while at the same time dissipating less power than the Gen1 device.

Gen1 SGTO near limit of operation at 13.5kA and 38.8V

To fully exploit the Gen2-on’s capability a low parasitic inductance and resistance module holding 8 devices in parallel was designed. The module design enables mxn arrays of modules to be connected in parallel (m) and in series (n). Three modules were assembled in series offering a 10kV DC rating with a volume of less than 100in3. The modules are triggered with a current transformer and have gate-emitter shunt resistors built in to hold the devices off. A photo of this 1x3 Pulse Switch Assembly (PSA) is shown in Figure 8.

10kV DC Pulse Switch Assembly (PSA) consisting of 24 Gen2-on SGTOs

The PSA includes voltage grading resistors to ensure the voltage is shared equally among the levels, along with a coaxial bus structure that offers a simple, yet low inductance connection to the PSA. The PSA was characterized by discharging a diode clamped 10mF capacitor with no load through the switch. A waveform and the I-V plot are shown in Figure 9.

58kA discharge through PSA

The I-V plot shows good linearity between I and V over the entire test range. Using this I-V plot, the PSA achieved a resistance of only 375mOhm and a diode knee (VD) of 3.63V! The parasitic resistance of the module electrodes was measured to be 26μOhm, meaning each Gen2-on device averages only 792μOhm and a VD of 1.21V.

Also demonstrated was a Gen2-off operating in sub-microsecond pulse mode. A 20 Ohm resistor was used as a load switched at 2kV to produce a 100A turn-off where the entire pulse lasted only 600ns, see Figure 10.

Sub-microsecond switching of a 6.5kV Si Gen2 SGTO

This first attempt at sub-microsecond switching delivered 80% of the energy to the load!

The promising preliminary results for Gen2-on and Gen2-off technology can be tailored to fit a broader range of applications through various post-process alterations making the technology a versatile tool for any high-voltage/high-current application. We expect superior results with our Gen2 SiC SGTOs as the minority carrier lifetime has been increased enough to allow for altering the lifetime profile after fabrication. The combination of thinner epi and engineered minority carrier lifetime profiles enables higher efficiencies in the sub-microsecond pulse range.


Extensive simulations were conducted, emphasizing the difficulty of achieving uniform current and heating distribution for pulse discharge events with large magnitudes of peak current.

Gen2-on and Gen2-off Si SGTOs have been demonstrated. The Gen2-on SGTOs provide at least a factor of 2 improvement of I2t capability over Gen1 devices without increasing the power dissipated, and the Gen2-off successfully transmitted a sub-microsecond pulse. A comprehensive study is underway to determine where Si versus SiC Gen2 devices will offer the best performance. Obviously SiC Gen2 devices offer higher breakdown voltages compared to Si devices, however the volume of the SiC Gen2 SGTO is roughly 7 times smaller for the same voltage and current rating compared to a Si Gen2 SGTO. Therefore, the DT for the same pulse is about 7 times higher. However, the physical properties of SiC permit larger temperature excursions (up to 4 times given SiC’s larger band gap and roughly 4x higher elastic modulus).

[1] V. Temple, “ThinPak Technology Shrinks Power Modules, Power Hybrids and Ultra-High Speed Switching Devices”, May 2000 PCIM feature article
[2] K. Ghosh and F McCluskey, “Reliability of ThinPak Assemblies in Thermal Cycling”, Nov. 2005 Proc. of IMECE


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