Tweet

Posted on 01 November 2019

A Fast Body Diode UniFET

Free Bodo's Power Magazines!

 

  

 

Analyzed and Tested under Zero Voltage Switching

The power supply market is dominated by majority carrier (high speed) switching devices. Fairchild has introduced a new highly optimized high speed fast body diode planar MOSFET (UniFET) for the SMPS market by reducing overall loss over regular 500V MOSFET.

By Sampat Shekhawat, Praveen Shenoy, Mark Rinehimer and Bob Brockway, Fairchild Semiconductor, Mountaintop, USA

 

Abstract

The power supply market is dominated by majority carrier (high speed) switching devices. Fairchild Semiconductor has introduced a new highly optimized high speed fast body diode planar MOSFET (UniFET) for the SMPS market by reducing overall loss over regular 500V MOSFET. By using this MOSFET, the power supply efficiency can be improved or other trade off such as cost reduction, size reduction or increase in power density can be realized. This MOSFET reduces the switching loss while keeping EMI in control. This MOSFET rated at 500V can compete with some of the super-junction MOSFETs. The new highly optimized MOSFET with fast body diode is designed to address the diode reverse recovery problem. This article also analyzes how diode behaves in third quadrant. The advantages of this fast body diode MOSFET body diode compared to super-junction fast body diode MOSFET are lower Qrr & Trr, better softness and high dv/dt. A special lifetime control further reduces Qrr and Trr and increases dv/dt ruggedness.

UNIFET

Fairchild has introduced the new optimized fast body diode cell structure DMOS technology known as UniFET for and SMPS industry. High efficiency requirement of SMPS are driving the demand of improved power devices. Server Power Supply, Telecom, Medical Equipments, UPS and Solar Inverters, and House Hold appliances has become reality. Solar and UPS inverter also requires fast body diode MOSFET. At present, generally high speed switches, such as conventional DMOS or SuperFET is the natural choice for these applications. The parasitic capacitances for the UniFET have been optimized and the Miller capacitance (Cgd) has been reduced in order to improve the performance. The output capacitance has also been reduced this has reduced the turn-off energy loss and at the same time the ringing in turn-off current has been reduced compared to other MOS technologies in order to reduce EMI. The gate ESR has been reduced to improve the dynamic switching performance of the device. The dynamic changes of parasitic capacitances are gradual and uniform which reduces ringing during turn-on and turn-off thereby reducing EMI. The specific Rdson of the UniFET has also been reduced by designing new optimized cell structure.

Zero Voltage Switching (ZVS)

High switching frequency allows reduction in power supply volume and weight. The key to increasing the switching frequency is to use soft switching topologies. ZVS topology operating at high frequency can improve the efficiency as well as reduce the size of the power supply. ZVS also reduces the stress on the semiconductor switch, improving the reliability. These advantages have made the high voltage high power Phase-Shifted Full Bridge ZVS PWM converter a very popular topology. The conventional power MOSFET body diode can cause device failure during switching due to unrecovered minority carriers. The Fairchild fast body diode UniFET has been targeted for this application. The diode recovery plays a vital role not only in above topology but also UPS and motor drive inverters as well as solar inverters. The reflected load to these inverters can also be non-linear and this causes third quadrent current in the MOSFET. The behavior of MOSFET body diode has been analyzed in this condition.

ZVS Topology Description

The difference between regular Full Bridge and PH-Full Bridge ZVS PWM DC-DC converter topologies control switching

The Phase shifted full-bridge zero-voltage switched (ZVS) pulse width modulated (PWM) converter (1) operating in excess of 100 kHz, shown in Figure 2, is a simplified schematic of the power circuit. The conventional full-bridge topology is switched off under hard switching conditions where switch voltage stress is also high. The conventional full bridge topology has been modified in two ways to achieve ZVS.

Phase shifted PWM full bridge ZVS DC-DC topology

First modulation is done by phase shifting two overlapping constant frequency square waves by using leading-leg and lagging-leg. Second, the soft switching (ZVS) is achieved to minimize or reduce the switching losses.

In contrast to turning on the diagonally opposite switches of the bridge simultaneously (i.e. Q1 and Q4, Q2 and Q3), a phase shift is introduced between the switches in the left leg (leading-leg Q1 and Q2) and those in the right leg (lagging-leg Q3 and Q4) as shown in Figures 1 and 2. This phase shift determines the operating duty cycle of the converter.

ZVS process

Zero-voltage turn-on is achieved by using the energy stored in the leakage and series inductance of the transformer to discharge the output capacitance of the switches through resonant action. The resonance forces the body diode into forward conduction prior to gating on the switch. Two different mechanisms exist which provide ZVS [3] for the lagging-leg and leading-leg.

1) During light loads, very little energy is stored in the primary side inductance L1. This causes the lagging-leg to turn on under a hard switching condition. As the load increases the energy stored in inductor L1 increases. This energy is used to charge the output capacitance of the devices that are turning off, and to discharge the output capacitance of the complementary device, thus forward biasing the free-wheeling diode. A switch with low output capacitance helps to achieve ZVS process at light load, improving the efficiency. The UniFET output capacitance has been reduced for this very same requirement.

2) For the leading-leg switches (Q1 and Q2), a different process provides the ZVS as explained below. Before Q1 turns off, the current in the primary reaches its peak value of the reflected filter inductor (L2) current. When Q1 is turned off, the energy available to charge the output capacitance of Q1 and to discharge the output capacitance of Q2 is the sum of the energy stored in the output filter inductor L2 and the primary side inductor L1. The energy stored in filter inductor L2 is available because the filter inductor current does not freewheel through the diode until the voltage across the secondary has fallen to zero. In this mode, even at lighter loads, much more stored energy is available to turn-on and turn-off the leading-leg switches than is available for the lagging-leg switches. Therefore, the body diode in the leading-leg, turn-on before the UniFET is gated on. This will reduce the turn-off loss of these switches.

In case of solar and UPS inverters also output filter is used to reduce THD. Under certain conditions similar situation can occur as explained for phase shifted full bridge PWM-ZVS application. In all these situations once the body diode conducts the UniFET can be gated-on. Once the UniFET is turns-on it carries current in the third quadrant.

Importance of free wheeling diode for this topology

The role of MOSFET body diode must not be taken lightly in the ZVS topology. Even with the reduced switching stress on the MOSFET, failure may occur because of a poor diode recovery. The failures have been reported [1, 2] at no or light load conditions. These failures result from the lagging-leg loosing ZVS at turn-on and turn-off forcing a hard switching condition. One potential failure mechanism is due to the CGD*dVDS/dt current. The resulting CGD*dVDS/dt current can cause VGS to charge above VTH (re-applied dVDS/dt). A shoot through condition will exist where both of the MOSFETs in the lagging- leg can turn-on and cause the leg to fail.

In a ZVS topology, the intrinsic body diode of the MOSFET is forced to conduct current before the channel of the device is turned on (Figure 3a). As current flows through the body diode, minority carriers are generated in both the N-epi and P body regions of the device (Figure 4b). When the gate of the MOSFET is turned on, most of the total current is diverted in the third-quadrant mode through the series path including the MOS channel, the parasitic JFET, and the drift region resistance.

a) Forward current through body b) Forward current through body & channel c) Reverse current through body and channel d) Reverse current through channel e) Reverse current through body diodes

In this mode, source-to-drain conduction occurs through both the body diode and the associated channel regions of the device (Figure 3b). The addition of this parallel current path begins to reduce injection of minority carries into the N-region of the body diode.

As the current in the primary transformer changes direction, current flowing through the associated channel regions also changes direction to a first-quadrant mode of conduction. This forces a small amount of reverse current in the body diode (Figure 3c), the small magnitude of the current being proportional to the low reverse voltage across the body diode. Since the injecting P body / N- junction is in parallel with the low resistance channel regions, the effective reverse voltage across the diode is only on the order of several hun- dred milli volts. This results in minimal removal of minority carriers from the heavily modulated N-region of the diode structure. In the absence of sufficient voltage to force significant carrier removal, only a relatively small reduction in minority carrier concentration due to lifetime-controlled recombination mechanisms occurs (Figure 3d).

When the MOSFET is turned off, the high reverse voltage results in the rapid removal of excess carries as the drift region begins to support the applied bias. Minority carries in the drift region at this time are swept across the P body / N-junction (Figure 3e). This rapid depletion results in a significant current density flowing through the P body region, a portion of which extends beneath the source of the MOSFET structure. The resistance of P doped region directly beneath the source of a conventional MOSFET structure is represented as Rb in Figure 4. If the magnitude of the current passing through Rb is sufficiently large to cause injection across the P-body / N+ source junction, the parasitic bipolar transistor may become active. This uncontrolled state of operation usually results in the destruction of the device.

Current conduction in the 3rd quadrant (drain voltage is –ve)

FRFET for ZVS Topology

The Qrr and Trr of the body diode should be low enough to provide complete minority carrier removal before the device turns-off. If this does not occur, the turn-off dVDS/dt of this device could turn-on the parasitic NPN transistor and forcing the transistor into secondary breakdown. The possibility of this failure occurring increases as the frequency is increased. The intrinsic body diode of the UniFET has been improved by reducing the Qrr and Trr as shown in Figure 5. The Trr has been reduced to 20%, Irrm has been reduced to 38% and Qrr has been reduced to about 15%. Following are the switch requirements for this topology:

  • Low body diode QRR and TRR
  • Low QGD & Low QGD to QGS ratio
  • Low Coss
  • High Threshold (VTH) voltage
  • Low conduction losses
  • Low internal gate ESR

Reverse recovery waveforms comparing fast body diode UniFET with competitive devices

Conclusion

A new fast body diode UniFET is presented for the switched mode power supply (SMPS), UPS and solar inverters market. By using the fast body diode UniFET, the power supply efficiency can be improved or other trade off such as cost reduction, size reduction or increase in power density as presented here. UniFET reduces both the switching and conduction losses over regular benchmark MOSFET. The turn-off switching loss was reduced by over 50% compared to fastest IGBT without compromising EMI. The conduction loss was also reduced drastically compared to regular benchmark MOSFET. When UniFET conducts current in third quadrant most of the current is carried by the MOS channel and very little current is carried by body diode. This helps in reducing the minority carriers in the drift region and hence improves reliability of operation.

 

References:

1) H. Aigner, et al., “Improving the Full-Bridge Phase –shift ZVT Converter for Failure-free Operation under Extreme Conditions in Welding and Similar Applications,” IEEE proceedings of IAS Society Annual Meeting, St. Louis, 1998.
2) L. Saro, et al., “High-Voltage MOSFET Behavior in Soft-Switching Converter: Analysis and Reliability Improvements,” International Telcommunication Conference, San Francisco, 1998.
3) J. A. Sabate, et al., “Design considerations for high-voltage high power full-bridge zero-voltage-switched PWM converter,” in Proc. IEEE APEC, 1990, pp. 275-284.
4) K. Shenai, et al., “Soft-Switched, Phase-Shifted Topology Cuts MOSFET Switching Stress in FBCs,” PCIM Magazine, May 2001.

 

 

VN:F [1.9.17_1161]
Rating: 0.0/6 (0 votes cast)

This post was written by:

- who has written 791 posts on PowerGuru - Power Electronics Information Portal.


Contact the author

Leave a Response

You must be logged in to post a comment.