Posted on 04 April 2019

A Formula for Higher Power Density: Inside the Power Clip 33 Dual MOSFET

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Several things, including the choice of silicon, IC placement, and power loop configuration led to the development of a dual power MOSET that delivers significantly higher power density in a smaller footprint.

By SG Yoon and Arthur Black, Fairchild Semiconductor

In power supplies, finding a way to increase power density - that is, producing more power per unit volume - leads to a number of critical design benefits, including smaller size, lower weight, higher efficiency, and lower material costs. It's no surprise, then, that many designers consider power density to be one of the most important metrics when selecting components for a power supply.

In a typical power train, one of the places where designers often look to improve power density is the power MOSFET. Semiconductor companies have made considerable advances in the power density of these devices in recent years, but silicon designers are always trying to improve on what already exists.

Recent work on a new device, the Fairchild FDPC8011S power clip 33 asymmetrical dual MOSFET, shows that there are still ways to make significant improvements in power density. This article looks at some of the things the power clip 33 design team considered in their search for higher efficiency in a smaller footprint.

Power Clip 33 dual MOSFET

Figure 1 gives a block diagram for the power clip 33 and Figure 2 shows that, compared to a power MOSFET of equivalent size (3.3x3.3mm), the FDPC8011S is able to handle an additional 8A of load with a TJ 6°C cooler.

Power Clip 33 vs competing 3.3x3.3 Dual MOSFET

The Power Clip 33 Package

The power clip 33 is a dual-die package that combines optimized figure-of-merit (FOM) silicon with a thermally optimized, low-inductance copper-clip interconnect package. Figure 3 shows key elements of the package construction.

Isometric view of Power Clip package

The high side (HS) MOSFET is placed drain down. The low side (LS) MOSFET is placed source down. The interconnect from HS source to LS drain is made via a large copper clip.

As shown in Figure 4, the power clip package achieves a dramatic improvement in parasitic resistance and inductance compared to traditional package designs such as the discrete Power 33, Power 56, and Power Stage 56 dual.

Power Clip package resistance and source inductance

Minimized Power Path Parasitics

For a synchronous buck power train to have optimal switching speed, the design must minimize package parasitic inductances in the high frequency (HF) switching path, which goes within the package from the V+ pin to SW to GND. The design must also minimize the physical distance between the V+ / GND input capacitor and the MOSFET package pins. The IC configuration in the power clip achieves these two objectives by using a drain-down HS MOSFET, a die-to-die clip, and a source-down LS MOSFET. This enables a minimum impedance switching path, with no bond wires, in the HF power switching path. The only interconnect in the power path is a low-inductance/low-resistance copper clip.

Enhanced Thermal Performance

To increase power density, the thermal performance needs to be optimized. On a typical PCB design, two large regions of board copper act as the power planes for V+ and GND. The drain-down HS and source-down LS power clip design enables large package footprint connections to these two major regions of copper. The copper clip supports excellent die-to-die thermal coupling. This enables a low RÈJA thermal impedance for both die, independent of the power split between them.

Advanced Silicon

The MOSFET technology used in this design is shielded-gate PowerTrench® technology. The HS and LS MOSFETs are both designed with low RSP (m?/unit area) and low gate charge (QGD) silicon. And both are devices with a very low FOM, which is defined as QGD*RSP.

Figure 5 shows Fairchild normalized RSP and normalized FOM (QGD*RSP) improvement over time.

RSP and FOM improvement over time

Fairchild has achieved a consistent and significant improvement in both of these parameters over time. Conduction loss is directly proportional to RDS(ON) and switching loss is directly related to QGD. For a given RDS(ON) MOSFET, as its FOM decreases, then QGD and switching loss will decrease. Fairchild’s design improvements have reduced both loss factors.

With the reduction in RSP (resistance per unit area), Fairchild is able to design for typical power train levels with a smaller sized die. This reduced die size also results in reduced QG and QGD. The smaller die size also allows usage of a smaller package, leading to reduction in package parasitics. The net result is a design with low switching loss and a small footprint.

Optimized layout for POL converter

Due to the minimized power loop area and board space used, the power clip 33 MOSFET package helps optimize the board layout and improve system efficiency. Figure 6 shows a board layout example with the power clip packaged device.

Board layout with Power Clip 33

This high-efficiency and high-frequency package allows for a very small footprint for the total power train design. MOSFETs, input cap, inductor and output caps all fit into a very small region. The small power train footprint uses a minimum switch-node area, which reduces the risk of electromagnetic interference (EMI) noise radiation from the SW node.

The exposed GND and V+ pads on the bottom of the package create an efficient thermal dissipation path from the MOSFET junction to the board copper and the ambient.

For the package to have minimal parasitics, and the best switching performance, it was critical to have a small loop for the loop formed between the input cap and the package V+ to GND pins. Optimized V+ and GND pin placement on the power clip package allows for the very close placement of input capacitor(s) to minimize the loop area and to reduce parasitic inductances and switching losses.

As shown in Figure 7, the size of the high-frequency switching loop is dramatically reduced with the power clip design. During a switching transition (LS-off to HS-on or HS-off to LS-on), current flow must rapidly shift from one MOSFET to the other. This commutating action occurs in the loop made up of the two power MOSFETs and the input capacitors. The switching transient in this loop is orders of magnitude faster than the ripple frequency of current in the output inductor. Therefore this is the loop that defines switching loss.

Size reduction in high frequency switching loop

With a discrete pair of MOSFETs, the switching current must flow through the full length of the HS and LS packages before returning to the input capacitor. With the power clip package, the current enters and exits on the same face of the package in a very tight loop, separated by a spacing of only two pins. In the discrete pair layout, HF loop size is limited by the package size of the MOSFETs. With the power clip package, loop size is now limited by the size of the input caps.


The power clip 33 is proof that there are still gains to be made in power density. Combining advanced silicon and improved packaging technology, the power clip 33 significantly reduces package parastitics and significantly surpasses the power density (A/mm2) performance of earlier discretes, including Power33/Power56 and Power Stage 56 dual combinations.

This article is an abbreviated version of a longer article that details lab measurements comparing the power clip 33 to traditional designs for efficiency, power loss, waveforms, temperature, and thermal impedance. To access the longer article, please go to “Power Clip 33 Asymmetrical Dual MOSFET with Increased Switching Frequency Solution in Point-of-Load (POL) Applications”, available in Fairchild Online Seminars.

Arthur Black, “Optimized Footprint Power Devices for Computing Applications”, Fairchild Semiconductor white paper. Paper not currently indexed on Fairchild website. Please contact for copy.


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