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Posted on 29 June 2019

A Look into the Future: Savings Potential in Inverter Design

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Cost savings with high-current PCBs and spring contact modules connected in parallel

The major manufacturers of frequency inverters in the range of 40kW to 90kW expect average market prices to drop by around 3% each year. To be able to stay competitive, drive and inverter manufacturers are having to optimize their products by way of costefficient production and reduced material costs. By cutting down on costly bus bars, reducing module costs and using quick and easy single-screw assembly, MiniSKiiP modules can be used to reduce costs for power modules, connectors and assembly by up to 27% over inverters based on standard modules with base plate and screw connections.

By Andreas Gießmann, Application engineer, Semikron Elektronik GmbH and Alexander Langenbucher, Product manager MiniSKiiP, Semikron Elektronik GmbH

 

High current PCBs replace bus bars

Up to now the use of a printed circuit board (PCB) for power and control terminals instead of copper bus bars was limited to inverter outputs of 50kW due to the maximum current carrying capability of the PCBs. Thermal measurements performed on MiniSKiiP modules show that with multi-layer PCBs with copper track thicknesses of up to 210µm or copper profiles [1], maximum continuous load currents of up to 170A are possible. The maximum rated current of power semiconductor modules for PCB mounting is currently 200A, i.e. inverters of up to a maximum of 50kW can be made inexpensively without bus bars. To save on assembly and material costs for 90kW inverters with high-current PCBs, the modules for PCB mounting have to be connected in parallel. The interesting aspects here were investigated on two MiniSKiiP 6-pack modules with 150A rated current.

Module positioning is decisive

Parallel connection of two three-phase MiniSKiiP inverters offers more leeway with regard to the physical layout of the modules and the connection of two phases. While the modules may be arranged horizontally or vertically to one another, for parallel connection of the phases, the question that arises is whether adjacent phases (U1-V1, W1-U2, V2-W2) or the same phases (U1-U2, V1-V2, W1-W2) are to be connected in parallel? To answer this question, the following conflicting optimisation criteria have to be taken into account:

• Minimisation of dynamic and static current asymmetry (lower derating)
• Low-inductive design and consequently low overvoltage
• Prevention of thermal hotspots on the PCB

The improvement of one of these criteria can lead to the deterioration of another at the same time. For instance, same-phase connection (U1-U2, V1-V2, W1-W2) and horizontal module layout is beneficial in terms of dynamic and static symmetry. The problem with this, however, is that the traces would cross over, causing hot spots on the PCB at these crossover points, see Figure 1.

Horizontal arrangement of modules with same-phase connection

Horizontal arrangement of modules with adjacent phase connection

An advantage of adjacent phase connection (U1-V1, W1-U2, V2-W2) and horizontal layout is the short traces on the PCB. However, considerable asymmetry between the parallel phases is to be expected since the current paths are different, as are the positions for the auxiliary emitters.

A vertical module layout with same-phase connection is virtually impossible to achieve since the module mounting hole limit the trace width too much. Furthermore, in this case, the module driver contacts would be intersected by the power paths.

Essentially, the triple-criteria optimisation concept above can only be implemented if the internal module current paths are known. Adaptations are normally not transferable to other case sizes or module layouts, but have to be made for the specific module.

Static symmetry

Static symmetry between two parallel paths is determined by the following factors:
• Threshold voltage and slope resistance of the parallel chips
• Parasitic inductances and resistance of wire bonds and DCB
• Connection to the DC link
• Position of the AC terminals U, V, W on the PCB

The threshold voltage and the slope resistance of IGBTs and diodes are subject to manufacturing-related variations. From a statistical point of view a current derating of 10% is sufficient in order to consider the maximum amp capacity of the chips [2].

The different-length DCB paths between the DC and U, V, W terminals result in different inductance and resistance values. The positioning of the DC terminal to the left of the MiniSKiiP module results in the shortest current path for the U1/U2 phase and the longest for phase W1/W2. Parallel connection of phase W1 of one module and phase U2 of the other produces the greatest deviation in DCB path see Figure 3.

Horizontal arrangement of modules: No limitation of trace width

In this case, the position of the AC terminal V between the paths can produce greater symmetry. Theoretically, the longer and narrower the PCB path, the greater is the resistance and inductance values of the trace between these two phases. This, however, is not particularly expedient with a view to avoiding thermal hotspots. For a given trace length, width and thickness, the position of the V terminal has a far better effect on the symmetry the closer this is moved towards phase W1.

On the face of it, this asymmetry of the V terminal counteracts the different DCB path lengths. An increase in clearance between the two modules brings about benefits with regard to thermal spreading and current symmetry. An increase in PCB size, however, means far higher costs if the dimensions of the PCB exceed the optimum number of panels per blank board. In parallel same-phase connection, particular attention is to be paid to DC link connection. For opposite phase connection, connection to the DC link can be designed such that it has an additional positive effect on the symmetry of the W1-U2 phases. Inside the module, phases U1-V1 and V2-W2 are connected in parallel. In this case, the DC link connection has no effect on current symmetry.

Dynamic symmetry

As regards dynamic symmetry, the aim is to reduce the different switching speeds between two switches to a minimum. The switching speed is determined by the gate resistance and the parasitic gate inductance, on the one hand, and by the position of the auxiliary emitter terminal on the other hand. The load current induces a current in the gate-emitter. Depending on the position of the auxiliary terminals, this current can have either an attenuating or accelerating effect. One gate and auxiliary emitter terminal is assigned to each switch in the MiniSKiiP module. The investigations on the 150A MiniSKiiP module showed that changing or replacing the auxiliary emitter terminals of the BOT switch brings about an improvement in dynamic symmetry.

The dynamic symmetry can be improved by changing auxiliary emitters

In addition, by using SMD inductances in the nH range in the gate path, the IGBT turn-on behaviour can be influenced considerably. An inductance in the gate path of the slower switching IGBT accelerates the IGBT turn-on behaviour and can have a positive effect on dynamic current symmetry. In this case, a separate turn-on and turn-off path is needed for this IGBT.

Thermal investigations

For the thermal investigations, two types of PCB which differed in the number of copper layers and layer thickness were used.

Design: 4-layered PCB with 105μm copper on the outer layers, no power path on the inner layers
Design: 4-layered PCB with 210μm copper on the outer layers and 105μm copper on the two inner layers

The measurements taken on the first design showed that close to the spring contacts thermal hotspots of 150°C develop on the PCB at a phase current of 170A. In this case, the heat sink temperature at a reference point directly beside the module is 100°C.

By using thicker copper layers, the temperature on the PCB is 30K lower for a phase current of 120A in the area close to the spring contacts. In addition, the modules were paralleled thermally, meaning that at 170A the heat sink temperature at the reference point can be reduced to below 80°C.

Calculations done by one PCB manufacturer of high current PCBs show that using copper profiles in PCBs can reduce the PCB temperature at these hotspots by up to 30K.

Comparison of heat sink and PCB temperature of 1st and 2nd design

Conclusion

Cost pressure on the inverter market will force manufacturers to switch over to less expensive PCB mounting for inverters in the 50kW to 90kW range. The necessary parallel connection of existing modules is possible but involves additional optimisation of the driver connection and power paths for every single module layout. This is complex and involves considerable time, as well as development and test capacities. To enable inexpensive inverters with PCB mounting to be developed more easily and more quickly, plans are underway to develop MiniSKiiP half bridges for fast single-screw assembly for applications with rated currents of up to 300A. This will enable material, module and assembly costs for inverter outputs of up to 90kW to be reduced substantially.

 

References:

1) Mauer, P., and Müller, D., "Fine-Pitch und hohe Ströme", www.elektroniknet.de, 2010.
2) Scheuermann, U. "Paralleling of Chips – From the Classical ‘Worst Case’ Consideration to a Statistical Approach”, PCIM Europe 2005, Conference Proceedings.

 

 

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