Posted on 17 July 2019

A New breakthrough in More Efficient Power Conversion

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Major design challenges of the deep trench epi filling technology

Since making a high efficiency power supply means saving energy bills in the places like the data centers, it is not surprising that power supply manufacturers are focusing on designing a high efficiency power supply. In computing area desktop PCs and laptop computers take huge portions of energy consumption. Therefore energy efficiency organizations have been very active in establishing guidelines for higher efficiency levels for power supplies. There is 80 PLUS program (, which unites electric utilities, the computer industry and consumers in an effort to bring energy-efficient technology solutions to the marketplace.

By Won-Suk Choi, Sung-Mo Young, and Denny Kim, Fairchild


One well-known organization is Climate Savers Computing Initiatives (CSCI, which was established in June, 2007 by Intel, Google, and others. It drives to improve energy efficiency and save power consumption of PC and server like IT equipments. Its goal is to reduce CO2 emission by 54 million tons per year for world wide IT equipments by 2010. Its focus activity is to develop how IT equipments to save power and educate how we can reduce power consumption. Specifically, it recommends two ways: one is to change power supply with a higher efficiency and one is for IT equipments and users that have a need to activate power saving settings like sleep or hibernate mode for PCs. It also sets technical specifications for high efficiency power supply as listed in its webpage. Under the rapidly changing circumstances that are encouraging energy-savings, most industry experts agree that new power technologies can play a critical role in the power conversion area. In this respect new products with state-of-the-art technology are always essential for better efficiency. A good example in high voltage devices is charge-compensated Super-Junction MOSFETs. Newly developed deep-trench filling MOSFETs utilizing charge-compensation theory have ultra low on-resistance and extremely fast switching speed, and can provide improved efficiency in switch mode power supplies.

Technological Considerations

The power losses of the switching device can be broken up into four parts: conduction losses, switching losses, turn-off state losses due to leakage current, and driving losses. In most switching power applications utilizing high voltage switching devices, the last two parts take a relatively small portion in total power losses. Between the two major power losses, the conduction losses can be reduced through realizing lowest possible on-resistance. The switching losses are determined by duration of switching transient, a period that current and voltage present simultaneously across the channel of the device. Obviously, faster switching transients reduce switching power losses. The switching device should have very low parasitic capacitances to be switched quickly. Therefore, considerable work has been done for improvements in on-resistance and parasitic capacitances. Among them, most remarkable achievement for on-resistance reduction was charge balance technology. The super-junction device utilizing charge balance theory is introduced to semiconductor industry ten years back, and it set a new benchmark in high voltage power MOSFET market. This technology has deep P-type pillar-like structure in the body in contrast to well-like structure of conventional planar technology. The effect of the pillars is to confine the electric field in the lightly doped epi region. Due to this p-type pillar, the resistance of ntype epi can be reduced dramatically compared to the conventional planar technology while maintaining same level of breakdown voltage. Therefore, this new technology has broken new ground in terms of the silicon limit regarding of on-resistance and achieved only one third specific on-resistance per unit area compared to planar processes. It is well-known that this technology also achieved unique non-linear parasitic capacitance characteristics, and therefore enabled reduced switching power losses.

Most commercially available super-junction devices adopted multiple epi layers to build the deep p-type pillar structure. In this structure, key design parameters for lower on-resistance are aspect ratio of ptype pillar and distance between unit cells. The common way for higher aspect ratio is adding more layers. However, the more layers means more complex process steps, and the increased process steps results in more expensive manufacturing cost. This structure is also hard to scale down for narrower cell pitch. As higher cell density is critical to bring about lower on-resistance it is another disadvantage of multiple epi layers technology. In order to realize better performance with lower cost comparing with existing technologies, it would be better to change rule of the game. By changing super-junction technology from multiple epi to deep trench filling it is possible to eliminate the existing drawbacks. This new technology firstly forms deep trench on n-type epi, and then fills it with p-type epi. In this way, the new technology has achieved much higher active cell density and simpler processes. For an example, new technology achieved number of epi process reduction by 67% compared to previous multi epi technology. Major design challenges of the deep trench epi filling technology are uniformity at both building the deep trench and filling it. If there are crystal defects or voids, they cause shift in electrical characteristics. Therefore, precise control in the processes is important to manufacturability. By overcoming all these challenges through device and process engineers’ endless efforts, the world first superjunction device utilizing deep trench epi-filling technology, the Supre- MOSTM came into the real world. Together with its fewer process steps, the on-resistance per specific area of SupreMOS is less than one fourth of standard power MOSFETs, and 40% smaller compared to previous generation charge-compensated Super-Junction MOSFET, SuperFETTM. The reduced on-resistance of the new technology is directly related to conduction losses in the systems. In addition, it opens a way to more compact system design since device with similar on-resistance can be packaged into smaller package.

Vertical structure of SuperFETTM (left) and SupreMOSTM (right), not in same dimensions

Efficiency Considerations

As a result of the reduction in the on-resistance per specific area, required chip area for same on-resistance becomes smaller with the new deep trench epi filling technology. This leads to very low gate charge and input capacitance. At 190mOhm, 600V rating, total gate charge of new device is only half of previous generation’s. Even though power losses in gate driver are relatively small in comparison with conduction or switching losses, reduced gate charge can contribute to efficiency improvement. It also has reduced Miller capacitance, capacitance between gate and drain. The smaller Miller capacitance gives even more reduced switching power losses in hard switching applications as voltage and current transitions mostly take place while the Miller capacitance is being charged or discharged. As a result, the new super-junction device can be operated with higher switching frequencies. Another important measure for the use at high frequency switching is a stored energy in the output capacitance. The energy is dissipated at every turn-on and causes power losses. When compared stored energy in the output capacitance, new device has approximately 30% less energy stored than in the case of previous generation at typical bulk capacitor voltages for switching power supplies. The benefits to switching losses are also verified in 600W continuous current mode power factor correction evaluation board. The system operating frequency is set to 120kHz, and STEALTH™ 2 fast recovery diode is applied as boost diode. As shown in figure 2, new device achieved about 30% reduction in switching losses and 0.7% higher power conversion efficiency. This represents a total power loss savings of more than 4.5W by simply replacing a single device.

Efficiencies and switching power losses in 600W CCM PFC

Another test has done with 70mOhm SuperFET in TO-3P and 85mOhm SupreMOS in TO-220. The 70mOhm is nearly lowest onresistance with multiple epi technology in big TO-3P package. Therefore parasitic capacitances are huge, and switching performance is far inferior to 85mOhm new device. The external gate resistances have reduced for the 70mOhm SuperFET from 30Ohm and 10Ohm for turn-on and off respectively to 10Ohm and 4.7Ohm considering its slower switching characteristics. However, 85mOhm SupreMOS still showed smaller switching losses and higher power conversion efficiency over all load ranges in 800W rated continuous current mode power factor correction block.

The reduced switching losses due to faster switching are very beneficial to power conversion efficiency during hard switching conditions.

Efficiencies and switching power losses in 800W CCM PFC

In soft switching converters, however, switching losses are minimized through zero voltage or zero current switching techniques. Therefore, most important parameter for soft switching converters is on-resistance. As stated above, new deep trench filling technology offers ultra low on-resistance and is the best candidate for soft switching converters. In addition to the on-resistance, there are other important electrical characteristics for soft switching converters. One is the stored energy in output capacitance. It influences switching losses at turn-on in case of hard switching, but also determines how much resonant energy is required in soft switching converters. As shown in figure 4, SupreMOS has the lowest stored energy in output capacitance at typical DC link voltage of switching power supplies.

Energy stored in output capacitance

Another important parameter is body diode reverse recovery characteristics Since many soft switching converters utilize the body diode to achieve zero voltage switching condition, hard commutation of body diode takes place during system operation. In that case reverse recovery characteristics of the body diode affect both efficiency and system reliability. The SupreMOS shows less reverse recovery charge than major competitors at same di/dt and forward current level. Also, it offers better reverse recovery dv/dt capability and smaller peak reverse recovery current. A competitive analysis between the SupreMOS and one of major competitors is shown in figure 5. The competitor part just failed but the SupreMOS withstands the stress at same conditions. Therefore, the SupreMOS can provide higher reliability especially under severe load transient or shorted output conditions.

Body diode reverse recovery characteristics


This article explored a new technology that has set a new benchmark not only in conduction losses but also in switching losses through low parasitic capacitances. This is nearly an ideal switch, and greatly improves the efficiency of power supplies. This is another leap forward in more efficient design and ultimately, in global sustainability.



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