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Posted on 25 November 2019

A Simple, Low-cost Technique for Compensating Isolated Converters

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The majority of flyback regulators today are controlled by IC´s with ever increasing integration of functions. Where the classic UCC regulators from Unitrode/TI expected the user to decide on voltage mode or current mode control, generate their own PWM ramps, compensating ramps (where appropriate) and current limit circuitry, the modern controller or integrated-MOSFET regulator takes care of all of these functions internally. As always there is a trade-off for the increase in simplicity, and the price paid is in flexibility.

By Christopher Richardson, Power Induced Design

This article focuses on a control loop compensation technique for modern ICs that include a fixed bias voltage and fixed internal pullup resistor for the phototransistor side of the optocoupler. When the pullup voltage and resistance are both fixed a hard limit for phototransistor current is established, and when the photodiode side of the optocoupler is biased from the converter´s output voltage the minimum mid-band gain in the compensator´s transfer function is also fixed. Several authors have discussed this limitation at length, in particular Christophe Basso in [1]. The most common solution is to power the photodiode side of the optocoupler with a separate, independently- regulated voltage. Creating this independent source requires more parts, using more PCB area and increasing cost. A simple alternative is shown in Figure 1, whereby a resistor is placed in series with an MLC capacitor of fairly high value - 1 μF or more - and this chain is connected from the phototransistor´s collector to ground. From a large signal perspective the R1-C2 branch is an open circuit, but in the small signal domain the capacitor is a short circuit, and the resistor can be selected as needed to reduce the compensator´s mid-band gain.

Simple Isolated Feedback and Control Compensation

If C2 were eliminated R1 and RP would form a pure resistor divider, and while this works quite well in simulation, in practice fixing the maximum voltage at the COMP pin of the control IC fixes the maximum duty cycle and in turn limits the maximum output power.

Limitations of Basic Type II Compensation

If R1 and C2 are removed from the circuit of Figure 1 then the small signal transfer function can be written in an intuitive, factored form as shown in [1]:

\begin{equation} G_{COMP}(s) = \frac{R_P}{R_A}\cdot \frac{CTR}{C1\cdot R_{TOP}}\cdot \frac{(1 + s\cdot C1\cdot R_{TOP}}{s\cdot (1 + s\cdot C_{OPTO}\cdot R_P)}\end{equation}

\begin{equation} f_{ZERO} = \frac{1}{2\pi \cdot C1\cdot R_{TOP}}\end{equation}

\begin{equation} f_{POLE\; 2} = \frac{1}{2\pi \cdot C_{OPTO}\cdot R_P}\end{equation}

This is a simple Type II compensation with a pole at the origin and a zero whose frequency can be set as desired. Pole 2 allows very limited control over frequency, especially when using control ICs such as the LM5001 from Texas Instruments, the ICE3AR series from Infineon or others where RP is the fixed internal pullup resistor. To make matters worse, the optocoupler´s parasitic output capacitance, COPTO is not adjustable and it changes with operating conditions. A network analyzer is the best tool to test this value. Pole 2 is generally used to cancel the ESR zero of the power stage, and/or to roll off the overall loop gain to ensure a wide gain margin. Adding resistance in series to RP or adding capacitance in parallel to COPTO can lower fP2, but there is no way to increase the frequency. In many cases the control loop design must accept this limitation and work around it.

Improving the Basic Type II Compensation

Returning to the circuit of Figure 1, if C2 is assumed to be sufficiently large so that it becomes a short circuit in the small signal domain then R1 and RP are in parallel. The simplified, factored transfer function and new Pole 2 then become:

\begin{equation} G_{COMP}(s) = \frac{R_P\cdot R1}{R_A(R_P + R1)}\cdot \frac{CTR}{C1\cdot R_{TOP}}\cdot \frac{(1 + s\cdot C1\cdot R_{TOP})}{s\cdot \bigg (1 + s\cdot C_{OPTO}\cdot \frac{R_P \cdot R1}{R_P + R1}\bigg )}\end{equation}

\begin{equation} f_{POLE\; 2} = \frac{1}{2\pi \cdot C_{OPTO}\cdot\frac{R_P\cdot R1}{R_P + R1}}\end{equation}

This provides the dual benefits of making mid-band gain adjustable to almost any value needed and also increases the frequency of Pole 2. Since lowering fP2 is relatively easy, the result is a "win-win" situation.

Example with CCM Flyback Converter

Continuous Conduction Mode regulators are most likely to benefit from this technique due to their power stage gain, which is higher than a DCM converter´s gain at the same operating point. The LM5001 Isolated Flyback Evaluation Board [2] is a good example of a CCM flyback when operated in the following conditions:

  • VIN = 24V, VO = 5V, IO = 1A, fSW = 250 kHz
  • PS2811-1M optocoupler: CTR = 150%, COPTO = 6,8 nF (tested using network analyzer)

Circuit Schematic for an Isolated, CCM Flyback Converter

Figure 2 shows a simplified circuit diagram of the LM5001 running as a flyback and Figure 3 shows a Bode plot of the power stage (duty cycle modulator plus output filter). SIMPLIS and other simulation tools or linear models (also available in reference [1]) can be used to predict the power stage response when a network analyzer is not available.

Gain (Blue) and Phase (Red) of the Power Stage, GPS

There are many different, equally valid design philosophies for compensating switching regulators. For this article the technique used will be to evaluate the gain of the power stage at the desired crossover frequency and then set the gain of the compensator to the negative of the power stage gain, thus ensuring that the overall loop gain is zero at the desired frequency. For a conservative, stable bandwidth of 5 kHz the gain of GPS is around 2 dB. RP is fixed internally in the LM5001 at 5 kΩ, and in order to ensure that at least 1 mA flows through the TL431 (see excellent discussion in [1]) the value of RA cannot go higher than 1,5 kΩ. Without R1 the minimum mid-band gain of the compensator would be:

\begin{equation} G_{MID-MIN} = 20log\bigg (\frac{R_P\cdot CTR}{R_A}\bigg ) = 20log\bigg (\frac{5k\Omega \cdot 1.5}{1.5k\Omega}\bigg ) = 14dB\end{equation}

The gain is simply too high - it pushes the overall loop bandwidth to around 25 kHz, where the phase margin would be almost zero owing to the load pole and right-half plane zero. The result would be an unstable regulator. Furthermore, without R1 the frequency of Pole 2 would be determined by EQ.3 and would be around 4,7 kHz. Such a low frequency would roll off the gain too soon, but more importantly would further reduce the phase margin - exactly the opposite of what is needed.

To lower the mid-band gain to the desired -2 dB and increase the frequency of Pole 2, R1 can be selected with the following equations:

\begin{equation} G_{MID} = 10^{\frac{-G_{PS-BW}}{20}} = 10^{\frac{-2}{20}} = 0.8V/V\end{equation}

\begin{equation} R1 = \frac{G_{MID}\cdot R_P\cdot R_A}{R_P\cdot CTR - G_{MID}\cdot R_A} = \frac{0.8\cdot 5k\Omega \cdot 1.5k\Omega }{5k\Omega \cdot 1.6 - 0.8\cdot 1.5k\Omega} = 944\Omega \end{equation}

Replacing R1 with a standard value of 1 kΩ fixes the gain to perfection and pushes the Pole 2 frequency out to 28 kHz, giving the overall control loop plenty of phase margin. The remaining component to be selected is C1, using EQ.2 to set fZERO equal to the load pole.

The final compensator and overall control loop Bode plots are shown in Figures 4 and 5.

Gain (Blue) and Phase (Red) of the Compensator, GCOMP

Gain (Blue) and Phase (Red) of the Control Loop, GLOOP = GPS x GCOMP

Conclusion

Figure 5 shows a stable control loop with a bandwidth of 5,24 kHz and 66º of phase margin. This simple technique to lower the compensator ´s mid-band gain and also increase the frequency of Pole 2 is already employed in many designs, but may not be fully understood. With the design philosophy and equations stated explicitly circuit designers can now stabilize an isolated converter for the price of one MLC capacitor and one standard thick film resistor. This comes at a considerable savings of cost, component count and PCB area over the development of a regulated voltage independent of the output voltage to power the photodiode side of the optocoupler.

List of Changes to LM5001 Evaluation Board

  • R8 = 1 kΩ, R13 = R16 = zero, R18 = R18 = 10 kΩ,
  • R14 = R15 = 1,5 kΩ, C15 removed, C16 = 33 nF

References
Switch Mode Power Supplies, Christophe Basso, McGraw-Hill 2008 SNVA221B: AN-1588 LM5001 Evaluation Board, Texas Instruments 2013

About Power Induced Design

PID was formed in 2013 to provide power electronics design, consultation and training to customers in Spain, the European Union and beyond. Our goal is to provide rapid, efficient service, from ground-up design to technical training to stepping in and solving problems when capacitors are blowing up and MOSFETs are smoking. The name Power Induced Design and our "roller coaster" logo are tributes to the initials PID, the lead-lag compensator used in the control loops of many switching regulators.

 

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