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Posted on 14 June 2019

Advantages of Double-Sided Cooling Concepts for Power Semiconductors

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A parametric study of the influence of chip mounting details on the junction temperature

Enhanced cooling concepts allow higher output power. New joining technologies (e.g. Ag sintering) allow higher operating temperatures without strong restrictions in reliability. Coming closer to the edge of silicon device operating temperatures, the on-chip temperature distribution might affect performance and should be considered in addition to the average junction temperature dictated by thermal resistance.

By Max H. Poech, Fraunhofer Institute for Silicon Technology ISIT, Itzehoe, Germany

 

Introduction

Conventional power semiconductors are joined on their entire back side by soldering or sintering to a DBC substrate (DBC = Direct Bonded Copper) in order to achieve good heat dissipation. The semiconductors top side is electrically contacted by means of wire bonds which do not provide a significant heat dissipation path.

A large area joint on the power semiconductors top side by soldering or sintering to a second DBC reduces the thermal resistance and increases the thermal mass adjacent to the chip. The latter is advantageous in case of pulse loads being significantly shorter than 1 s. Since the semiconductors top side cannot be contacted at the entire surface due to the gate contact and isolation requirements, cooling to both sides will usually not result in half of the thermal resistance. Instead, it is typically reduced by about one third, which is equal to an additional heat dissipation of about 50% via the top-side connection.

Schematic view and cross sectional view of a double sided cooled, double DBC assembly (“slot module”, FhG IISB), with semiconductor chips joined between the DBCs [1]

The position of the semiconductors top side contact areas may have an unfavorable influence in particular on the temperature distribution on the chip. These effects are described with the following model calculations.

Model calculations

Utilizing an axisymmetric approximation, the model describes the DBC - Si-chip - DBC stack, with 0.3/0.38/0.3 mm Cu-Al2O3-Cu DBCs, 0.2 mm thick Si and Ag sinter joints (30 μm). This sort of model has successfully been used before [2] with the advantage of short calculation times suitable for parameter variations. The lateral dimensions represent 10x10 mm2 Si, 15x15 mm2 Cu (DBC top side) and 25x25 mm2 DBC. Heat supply is performed by a constant power loss density in the upper 40 μm Si, the heat is removed to ambient temperature with a heat transfer coefficient of 5000 W m-2 K-1 acting at the DBC outer surface, which corresponds to a moderate water cooling. In figure 3 to 5, showing the temperature distribution within the stack, the temperature rise against ambient is shown. Mainly, the chip top contact area has been varied in size (percentage of chip area) and position.

Results

The results of the model calculations are presented in Table 1 and Figure 2.

Results of the model calculation, thermal resistance RTH, maximum and minimum chip temperature, each divided by the mean value by area of the chip temperature, as well as their difference.

Results of the model calculations, spread of relative chip temperatures (columns) and thermal resistance RTH (symbols)

With good heat dissipation, there is always a temperature gradient from the chip center to the edge [3], due to lateral heat spreading in the substrate (Figure 3). Indeed, the better the cooling, the wider is the temperature distribution on the chip, valid for single and bothsided cooling (Table 1, Model 1, 2 and 4, Figure 2). The local junction temperature is known to affect reliability of conventional assemblies [4].

With the 4-fold heat transfer coefficient of 20000 W m-2 K-1 acting at the DBC bottom side, which implies significantly improved flow conditions achieved by a more sophisticated cooling structure, one can achieve a thermal resistance with single-sided cooling being equal to double-sided cooling, however bought with a much higher temperature spread on the chip (Table 1, Model 2). Thus, double-sided cooling appears to be efficient even with moderate effort in cooling channel design.

The non-relevant single-sided cooling via the partially joined top side (Table 1, Model 3) provides an unacceptable high thermal resistance together with an inadequate temperature spread (thus not included in Figure 2).

The results further show, that the layout of the chip top contact can be used to effectively reduce the width of the temperature distribution (Table 1, Model 5 to 8, Figure 4). Contacting the chip top side at an area less than 50% centrally favorably affects the width of the temperature distribution, with an optimum in terms of homogeneous chip temperatures at about 20 - 25% of the chip area at a slightly poorer thermal resistance.

If the chip center is left out in the chip top side contact (Table 1, Model 9, Figure 5), i.e. the top contact compares to a ring shaped area on the chip surface, then the temperature distribution is considerably wider. In fact, in case of a temperature rise of 150 K at 25°C cooler temperature, the mean junction temperature of 175°C will be encountered, but locally a semiconductor temperature of 244°C will be caused by the temperature distribution, which is assumed to be functionally critical for Si semiconductors.

Discussion

As has been shown, the chip top side contact shape can be used as an efficient design parameter to optimize thermal performance in double-sided cooled assemblies. Since the heat source in the semiconductor is generally assumed closer to the Si chip-top side, the assembly is not strictly symmetric, i.e. the single sided cooling is even slightly worse than twice the thermal resistance of the double-sided cooling assembly when assumed ideal (Table 1, Model 1 and 4).

The axisymmetric model overestimates the minimum chip temperatures, because the colder corners are not considered. Therefore, the width of the temperature distribution on the chip is larger, but uncritically extended to lower temperatures in reality. Experience has shown, that the assessment of the critical high temperatures in the chip centre is largely mapped correctly. Although the discretization in the model is relatively coarse, with the grid lines shown in the graphs of the temperature distributions, the strong influence of the varied parameters is clearly visible.

Temperature distribution within a conventional assembly Sichip on DBC, single sided cooling, bottom, PL = 45 W (left = axis of symmetry at chip centre; right = DBC edge)

Today, it is not yet fully understood, how the width of the temperature distribution on the chip affects its electrical performance. In addition to this thermal aspect, the electrical conductivity of the metallization is relevant in terms of current distribution [4], which in particular may result in the case of over-current to a local increase of the power loss and, thus, can cause a semiconductor defect.

Temperature distribution within a double-sided cooled stack assembly DBC-Si-DBC, Si top contacted centrally at 22% of chip area, PL = 90 W.

In almost all cases calculated here, the maximum DBC temperature on the cooler side is actually higher than the average chip temperature, and in the other cases only slightly lower. Thus, making use of the possible junction temperature, the water cooling circuit will convert locally to an evaporation cooler, a fact being less critical with regard to thermal resistance, but with regard to a corrosive attack (cavitation) or to a formation of deposits from possible contamination in the cooling medium [2]. Boiling can be counteracted with an increased pressure in the cooling circuit (for water about 5 bar for 150°C, nearly 10 bar for 175°C), while the common ethylene glycol admixture increases the boiling point only a few degrees.

Conclusion, Summary

Of course, this parametric study is not intended to be exhaustive, but it already shows that top benefits can be achieved with double-sided cooling concepts, or significant disadvantages have to be taken into account, depending on the contact area on the chip top side.

With a centered top contact, a low thermal resistance combined with an almost homogeneous junction temperature can be achieved.

Prerequisite for a favorable assembly concept is, of course, that the semiconductor manufacturer provides the chip layout and the metallization in such a manner that the gate contact is placed in a corner, and that the surface can be joined in a suitably large, centrally placed window. For direct water cooling acting on the DBC, evaporative cooling is expected at higher loads, which has to be considered and optimized in terms of coolant medium and flow conditions.

Temperature distribution within a double-sided cooled stack assembly DBC-Si-DBC, Si top contacted ring shaped with 46% of chip area, 22% centrally are not connected, PL = 90 W.

 

 References:

1) BMBF-Projekt UltiMo, "Ultrakompaktes Leistungs-Modul höchster Zuverlässigkeit“, Forschungsverbundprojekt "Leistungselektronik zur Energieeffizienz-Steigerung,“ (LES) innerhalb des Förderprogramms "IKT2020“, Projektträger VDI Technologiezentrum GmbH.
2) Max H. Poech, Modelling of Thermal Aspects of Power Electronic Assemblies, Proceedings IMAPS Nordic Annual Conference, Helsingør, Denmark, 26-28 September 2019, 120-125.
3) Uwe Scheuermann, Ralf Schmidt, Investigations on the VCE(T)- Method to Determine the Junction Temperature by Using the Chip Itself as Sensor, PCIM Europe 2009, 802-807.
4) Max H. Poech, Power Electronics Reliability - the Materials Behaviour is the Key, PCIM Europe 2010, 350-355.

 

 

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