Posted on 02 November 2019

CoolSiC™ JFET Driver for Direct Drive Topology

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Last year the CoolSiCTM JFET with its low power losses, high reliability, and robustness had been in-troduced. Now the first dedicated galvanically isolated unipolar JFET gate driver is presented. The driver is optimized for the Infineon normally-on SiC JFET family utilizing the Direct Drive JFET concept

By Marc Buschkühle, Infineon Technologies AG

To operate these emerging CoolSiCTM JFET to their full efficiency potential and at the same time safe, Infineon has developed and refined the Direct Drive JFET concept.

The principal idea is to permanently turn on the low voltage MOSFET in normal operation. Then, the JFET is controlled by means of its own gate drive stage performing the desired switching caused by the logic control signal. Compared to a conventional Cascode circuit, the Direct Driven JFET approach allows lowest dynamic losses combined with a good controllability of the JFET switching transients.

In figure1 the schematic of an half bridge module with direct drive technology, the Easy1B module itself and an exemplary chip arrangement can be seen.

Direct Drive CoolSiCTM JFET

Existing driver solutions for safe and efficient operation based on the Direct Drive JFET concept (Figure 2) are rather costly and complicated as they require multiple chips that consume large PCB area. With Infineon’s JFET driver only one driver chip with few external components is needed. The driver is an advanced galvanically isolated single channel normally-on SiC JFET gate driver tailored to the Infineon CoolSiCTM JFET family offered in a DSO-16, 150mil [1EDI30J12CL] and DSO-19, 300mil [1EDI30J12CP] package.

1EDI30J12CL driver solution

Driver topology

The 1EDI30J12Cx single channel CoolSiCTM JFET Driver contains an input and output chip in one package with communication between the two chips performed by a coreless transformer. This corless transformer driver provides galvanic isolation of at least 1200V and common mode transient immunity of at least 100V/ns. A block diagram of the driver is shown in Figure 3. The input chip has two input signals, IN and EN, where IN is the control signal to control the gate of the JFET in a non-inverting manner and EN is the enable signal of the JFET Driver. When the input chip is disabled by pulling the pin EN low or by an undervoltage-lockout (UVLO) event, a turn off command is sent to the output chip to turn off the JFET before the input chip powers down.

1EDI30J12Cx SiC JFET Driver block diagram

A low voltage PMOS has been chosen instead of an NMOS as it ensures a better dynamic JFET be-havior. Using a NMOS adds inductances inside the gate charge loop form which slows down the JFET switching and therefore increases switching losses. A PMOS also makes the integration of the two drivers onto a single IC easier because the two transistors then have the same reference node.

To reduce the switching losses when using an NMOS, the power supply for the JFET driver can be arranged but then the integration of the two drivers into one IC would become very difficult due to the di/dt induced voltage ringing across the NMOS while the JFET is switching.

The output chip has two rail-to-rail gate drivers that are driven between VCC2 and VREG, JFDrv for the JFET, MDrv for the MOSFET. VREG is regulated by the internal voltage regulator to -19V seen from VCC2 so as to maintain the driver voltage between the pinch-off and punch-through voltage of the Infineon SiC JFET family, see Figure 4. The input voltage of the regulator VEE2 can vary from - 28V to -22V referred to VCC2 with full power supply rejection ratio (PSRR) performance of the regulator.

The JFDrv driver is a 3A peak driver with at least 2A driving capability with less than 4V voltage drop in both directions. If the drive strength is insufficient, i.e. when several JFETs are parallelized or a JFET module is used, a booster can be added.

CoolSiCTM JFET driver from Infineon

Start up/shut-down behaviour

The driver is built to handle various startup scenarios so that the user does not have to worry about which power domain comes up first, VCC1, VEE2/VREG, or the DC-link potential of the power con-verter that utilizes the switch.

For the output chip the most straightforward approach is to apply VEE2 first while the PMOS gate is kept high and the JFET gate is kept low regardless of the data coming from the input chip until the UVLO turn-on level is crossed. Then the PMOS is permanently turned on and the JFET can start to switch according to the commands coming from the input chip. At power-off or a power supply failure, the JFET gate is pulled low when the turn-off level of the UVLO is crossed and thereafter the PMOS is turned off.

A more involved scenario arises when a voltage is applied to the switch first (see Figure 5). In this case, all voltages are initially zero when the voltage across the switch rises to 200V between JFET drain and PMOS drain. A voltage source is connected directly to the switch for demonstration purposes in this measurement. The integrated diode D1 (see Figure 3) and the externally turned off PMOS M1 (see Figure 3) pinch off the JFET much like in the conventional cascode so that the switch will behave like a normally-off switch.

As soon as the JFET is pinched-off, the JFET acts as a linear regulator powering the driver chip that will see the pinch-off voltage of the JFET at VCC2-VREG and VCC2-VEE2 independent of the voltage over the JFET and PMOS drains.

Safe operation - A system start up measurement


A new dedicated galvanically isolated unipolar single channel gate driver for Infineon’s normally-on SiC JFET family has been presented. The driver manages the normally-on SiC JFET in a way that makes the total solution as safe as a normally-off switch with a considerably lower count of external components and PCB area compared to alternative solutions. Additionally this driver incorporates a unique control that allows powering the drivers through bootstrapping which so far has not been possible with normally-on switches.

• Karl Norling, Christian Lindholm, Dieter Draxelmayr: 1st Commercial
SiC JFET Driver for Di-rect Drive JFET Topology.
• Bjoerk, F.; Treu, M.; Hilsenbeck, J.; Deboy, G.; Domes, D.; Rupp,
R.: 1200V SiC JFET in Cas-code Light configuration: comparison
versus Si and SiC based switches. Domes,
• D.;Zhang, X.: Cascode Light – normally-on JFET stand alone performance
in a normally-off Cascode circuit..
• Domes, D.; Messelke C.; Kanschat, P.: 1st industrialized 1200V
SiC JFET module for high en-ergy efficiency applications.


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