Tweet

Posted on 17 July 2019

Coordinated Circuit Protection for High-Speed USB Applications

Free Bodo's Power Magazines!

 

 

 

USB 3.0 applications need circuit protection on the jack

USB (Universal Serial Bus) has become the most popular and pervasive connectivity technology for portable electronics. As the adoption of this standard has grown, USB connected devices have begun to cover a broader range of hardware applications. The evolution of USB protocols such as USB Charger and USB 3.0, or “SuperSpeed USB,” has created a demand for more robust and reliable circuit protection techniques. In addition to raising power-delivery capabilities, the new protocols have increased data-rate speeds and have made low-capacitance ESD (electrostatic discharge) protection of the bus more important than ever.

By Kedar Bhatawadekar, Technical Marketing and Product Application Engineer Tyco Electronics’ Raychem Circuit Protection Products

 

The trend toward using USB’s power capabilities to charge portable devices has resulted in a demand for industry-standard approaches for protecting charging systems and the connected devices. The most significant change in USB 3.0 is that an additional physical bus has been added in parallel with the existing USB 2.0 bus.

This article describes coordinated circuit protection techniques that can help protect USB ports and portable electronics against damage from overcurrent, overvoltage and ESD transients.

Higher Current, Higher Risk

Although power via USB has been in use for some time, the new USB Charger standard dramatically increases the amount of current that can flow to a USB device – to a new maximum current rating of 1.5A (as compared to 0.5A for USB 1.0 and 2.0).

The new USB 3.0 specification increases the amount of current that can flow to a USB device – from a maximum current rating of 0.5A to 0.9A. A new Powered-B connector allows one USB device to charge another device by supplying current up to 1.0A. Since overcurrent conditions can affect the power bus, overcurrent protection is necessary on all power sources (e.g., hosts, hubs, and Powered-B devices). Overcurrent protection is also required per UL60950.

Overvoltage transients are generally a result of ESD and may occur on both the power bus as well as the data lines. Although modern ICs are protected to up to 2000V, a human body can easily build up static charge that ranges up to 25,000V. In I/O port protection applications, a very-low-capacitance ESD device with fast clamping and recovery response is required on the data lines.

Overcurrent Protection Requirements

The USB Charger and USB 3.0 specifications require that end-user-accessible, powered connectors implement overcurrent protection. The overcurrent protection device must be resettable without requiring user mechanical intervention, and its preset trip limit must be above allowable current transients in order to avoid false trips.

Polymeric positive temperature coefficient (PPTC) devices, such as the PolySwitch™ device, have demonstrated their effectiveness in a variety of high-speed interface applications. Like traditional fuses, they limit current after specified limits are exceeded. However, unlike a fuse, PPTC devices have the ability to reset after the fault has been cleared and the power cycled. Their low resistance, fast time-to-trip and small form factor have made them the preferred method of overcurrent protection in many powered bus architectures.

The PPTC device is made of a composite containing a conductive filler, such as carbon black, that provides conductive chains throughout the device. The PPTC device exhibits low-resistance characteristics under normal operating conditions, but when excessive current flows through the device, its temperature increases and the crystalline polymer changes to an amorphous state.

As shown in Figure 1, this transition causes the polymer to expand, breaking the conductive paths inside the conductive polymer. The change causes a dramatic increase in the device’s resistance, which reduces the amount of current that can flow through the device to minimal levels. The PPTC device will remain in this state until the fault is removed. Once this occurs, the device cools, the carbon chains reconnect and the device returns to a low-resistance state.

 How the PPTC device works

Current limiting in a fault condition helps prevent circuit damage and system-wide voltage droops, and, with individual port protection, allows the remainder of the USB bus to continue functioning even if one port is short-circuited. As shown in Figure 2, the critical device parameters in USB applications include time-to-trip, resistance, and power dissipation.

Response of a PolySwitch nanoSMD device exposed to a 0.5 ohm fault

PPTC devices are resistive series elements on the USB power bus. Resistance, in this case, applies to a device when it is not in the tripped state. As such, the lower the PPTC device resistance, the lower the voltage drop between the power supply and the USB output pin during normal device operation.

Hold current is the highest steady-state current that a device will maintain for an indefinite period of time without tripping. Hold current is temperature dependent and the designer must consider the maximum ambient temperature that the device will be exposed to. Generally speaking, lower hold currents imply higher resistance and faster trip time, while higher hold currents offer lower resistance. For lowpower applications, a device with the lowest possible hold current should be selected.

Time-to-trip characterizes the speed at which a PPTC device will trip in a fault condition. Time-to-trip values are highly dependent on device design, device size, hold current, and can also be influenced by board layout where large trace sizes or pads functioning as heat sinks will increase time-to-trip.

Tripped power dissipation, or leakage current, is another important consideration for low power designs. After a PPTC device is tripped, it will stay latched in a high-resistance state, continuing to pass a small trickle current (dissipate power) until it exits the tripped state. The lower this trickle current, the lower the power drain on the system in a fault condition.

Transient Protection Design Considerations

Transient protection is critical when designing peripherals that may be powered off computer buses and automotive power buses. On computer buses, inductively generated voltage spikes can exceed 8V on the 5V line and 16V on the 12V line, which can damage unprotected peripherals. With the advent of low-cost, third-party AC-to-USB converters and car cigarette lighter-to-USB converters, the potential for transients to be seen on computer buses continues to increase.

Traditional clamping diodes represent the simplest overvoltage protection solution. However, in order to withstand the potential power output of a non-approved charger, while still providing resettable protection, this diode must be capable of dissipating nearly all of the power that a non-approved charger could deliver. The resulting protection solution would therefore require both a large diode and significant heat-sinking infrastructure, thus making it an impractical choice.

In addition to the risk of connecting the wrong power supply, voltage transients can also damage a portable device. Although typical computer power supplies provide regulated lines at 5V +/- 5%, and 12V +/-5%, under certain circumstances, the voltage at these lines may exceed 5.25V, and 12.6V, causing potential damage to the system or unprotected peripherals. Voltage spikes can occur when there is inductance in the power bus and a rapid change in current occurs.

This change can result from a hot disconnect of a peripheral, an internal system shutdown, or other internal power fluctuations. Inductance can be designed in with magnetics, but can also be generated by long cables and other power bus artifacts. The more inductance in the power bus, the worse the voltage spike seen by the peripheral is likely to be.

Polymer-enhanced Zener Diode Helps Protect Powered Ports

As shown in Figure 3, polymer-protected Zener diode micro-assemblies, such as a PolyZen™ device, incorporate a stable Zener diode for crisp voltage clamping and a resistively non-linear PPTC layer.

Tyco Electronics’ PolyZen device helps provide input power protection for portable electronics

The PPTC layer responds to either diode heating or overcurrent events by transitioning from a low- to highresistance state. In the event of a sustained high-power overvoltage condition, the tripped PTC element limits current and generates voltage drop to help protect both the Zener and the follow-on electronics – effectively increasing the diode’s power handling capability.

This device is particularly effective at clamping and smoothing inductive voltage spikes. In response to an inductive spike the Zener diode element shunts current to ground until the voltage is reduced to the normal operating range. In the case of a wrong voltage power supply, the device clamps the voltage, shunts excess power to ground, and eventually locks out the wrong supply, as shown in Figure 4.

Polymer-enhanced Zener diode clamps and smoothes inductive voltage spikes

The relatively flat voltage vs. current response of the polymerenhanced Zener diode helps clamp the output voltage, even when input voltage and source currents vary. Simply put, the polymerenhanced device helps provide coordinated protection with a component that protects like a Zener diode, but is capable of withstanding very-high-power fault conditions without requiring any special heat sinking structures beyond normal PCB traces.

ESD Protection for High-speed Ports

Overvoltage transients are often the result of ESD and may occur on the power bus as well as the data lines. At the high-speed data rates of USB Charger and USB 3.0, the parasitic impedance of traditional protection devices can distort and deteriorate signal integrity.

The existing USB 2.0 protocol allows for data transfer rates of up to 480Mbps and supports plug-and-play, hot-swappable installation and operation. In comparison, the USB 3.0 specification allows for data transfer rates of up to 5Gbps, with fall-back support for the lowerspeed USB 2.0 specification.

USB 3.0 adds four new pins to the connector to support the new SuperSpeed interface: USB3_TX (differential pair) and USB3_RX (differential pair), as shown in Figure 5.

The new SuperSpeed interface lines and the legacy USB interface lines

The SuperSpeed interface of USB 3.0 requires lower-capacitance ESD protection than that of USB 2.0. Adding very-low-capacitance PESD devices can help minimize insertion loss in order to meet eye diagram requirements of USB 3.0. With a typical capacitance of 0.2pF, and flat insertion loss to >6GHz, PESD devices are capable of supporting USB 3.0 application requirements and handling numerous ESD transients.

Compared to most traditional MLV (multilayer varistor) or TVS (transient voltage suppression) diode technologies, PESD devices provide lower capacitance, and their low-trigger and low-clamping voltage also help protect sensitive electronic components.

These devices are applicable for ESD protection on both USB 2.0’s high-speed D+ and D- signal lines and USB 3.0 SuperSpeed signal lines. Adding PESD devices to the circuit protection scheme yields protection levels that meet the specifications of IEC62019-4-2, which specifies 8kV (typ)/15kV (max) for contact mode and 15kV (typ)/25kV (max) for air discharge mode.

Coordinated Circuit Protection

PPTC devices can be used for current limiting in USB 3.0 host applications, USB 3.0 hub applications, USB charging applications, and USB3.0 Powered-B applications. As shown in Figure 6, installing a PolySwitch device on the VBUS port of a USB power souce limits current in the event of a short circuit, prevents overcurrent damage caused by a sudden short circuit downstream, and helps achieve UL60950 compliance.

Coordinated host-side protection solution

Because USB 3.0 increases normal operating current and current limits, USB overvoltage protection devices designed for traditional 0.5A ports may be inadequate for the new USB 3.0 specification of 0.9A per port. If a 0.9A host disconnects, high-voltage inductive spikes can be generated that may negatively affect the devices left on the bus. A well-designed bus will absorb these spikes, thereby protecting devices from exposure to them.

For USB 3.0 devices, the PolyZen device can be placed on the VBUS of the USB input port, the DPWR port of Powered-B plugs, and the barrel jack power port and VBUS input of USB hub devices.

It should be noted again that USB 3.0 will not support bus-powered hubs and will only support self-powered hubs. A power source is now needed to power-up all ports of the hub in USB 3.0 applications. If a DC power connector is used at the input to the hub, a circuit protection device may be warranted to help protect the hub electronics from damage caused by overvoltage events, from an unregulated or incorrect supply, reverse voltage, or voltage transients.

Figure 7 shows how installing a PolyZen device on the VBUS and six low-capacitance PESD devices on a typical USB circuit can help provide a coordinated overvoltage solution.

Coordinated device-side protection solution

Conclusion

The new USB specifications promise faster, more power-efficient electronic equipment. However, these higher-current applications will require more robust circuit protection. By utilizing a coordinated circuit protection approach, manufacturers can enhance customer satisfaction, reduce warranty costs, and help the equipment comply with applicable safety and performance standards.

Note: PolySwitch and PolyZen are trademarks of Tyco Electronics

 

Silicon ESD Devices Help Conserve Board Space

Silicon ESD image

As integrated circuits shrink, so does their ability to withstand ESD stress, thereby increasing the risk of circuit damage. New micro-USB and micro-HDMI connections in portable electronics are excellent examples of applications where miniature surfacemount passives can help provide a robust, space-saving and cost-effective ESD protection solution.

The small footprint, bi-directional technology and ultra-low capacitance of new silicon ESD (SESD) devices make them particularly well-suited for portable electronics applications. The 0201-sized SESD devices are approximately 70 percent smaller than prior generation 0402-sized devices and help provide protection and improve reliability of mobile phones, MP3 players, PDAs, digital cameras and other mobile devices.

The SESD device’s miniature footprint – measuring a mere 0.6mm x 0.3mm x 0.3mm – offers designers flexibility in spaceconstrained applications. Ultra-low capacitance (0.6 picofarad), low insertion loss and (<0.5dB up to 3GHz) and high linearity of voltage vs. frequency helps minimize signal degradation on veryhigh- speed data lines, such as USB and HDMI, or low-voltage antenna ports.

Bi-directional operation allows placement on the printed circuit board (PCB) without orientation constraint and won’t clip signals that swing below ground. Designed to withstand IEC62019-4-2 ESD test pulses, the SESD device can help protect sensitive integrated circuits (ICs), as well as keypads, power buttons, speakers and microphone ports in portable electronics.

 

 

VN:F [1.9.17_1161]
Rating: 3.0/6 (1 vote cast)
Coordinated Circuit Protection for High-Speed USB Applications, 3.0 out of 6 based on 1 rating

This post was written by:

- who has written 791 posts on PowerGuru - Power Electronics Information Portal.


Contact the author

Leave a Response

You must be logged in to post a comment.