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Posted on 03 July 2019

Deadly Sins in Power Electronics

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Different life expectancies can be assumed for different design technologies

Power semiconductors can be found in many applications providing high performances in a targeted, managed and reliable manner. Great effort is made in development departments to ensure that the power electronics devices developed there meet the requirements of practical applications. In many cases, development costs incurred this way can be considerable, as can the costs for hardware.

By Werner Bresch; GvA

All the more remarkable then to note that sometimes inadvertence or minor design negligence thwarts these efforts. In many cases, this can be attributed to the requirement to minimise manufacturing costs for the design – with the result that a few cents are saved at a certain point at which perhaps no savings should have been made.

Clamping systems for power semiconductors, regulated pressure brings performance.

It should really be accepted that this issue is actually old hat. But practical applications are demonstrating time and time again that approaches are being used, particularly with clamping systems, which, to put it cautiously, are dubious to say the least. Often, designs in which only one tension bolt is used for two disc cells (which are popular, for example, in the W1C AC controller configuration) materialise as a result of cost pressure. A well made clamping device simply requires a slightly higher financial commitment which pays for itself quickly if potential failures in the field can be prevented as a result.

To clarify why a clamping system must satisfy certain minimum requirements, it is really important to be familiar with the internal structure of a disc cell. Inside the disc cell is a silicon wafer which is either alloyed onto a molybdenum disk on the anode side or which lies loosely between two molybdenum disks as a so-called “free pressure contact”. In turn, these molybdenum disks lie between the thick copper anodes and cathodes of the disc cell housing. There is often a thin foil (e.g. silver) between the molybdenum and copper which acts as a ductile intermediate layer between the individual internal materials and which is important in attaining the inner thermal transition resistances specified in the data sheet. Disc cells are available today with pressure contact diameters of approx. 20 mm to approx. 150 mm. The overhead associated with a 150 mm pressure contact is of course higher than with a 20 mm pressure contact.

The following are required from the clamping devices/assemblies:

Reliable electrical insulation from the anode to cathode side (dependent on the inverse voltage of the power semiconductor deployed and the resulting application voltage).

Reliable application of the contact pressure required, which can now be up to approx. 180 kN depending on the size of the power semiconductor. The pressure thrust bearings may not bend under the tensile stress - the tension bolts must be able to withstand the tensile stress. The spring elements may not compress in all the way.

The thrust bearings, pressure distributors, insulators and the cooling units on the anode/cathode sides must have sufficiently good pressure- time stability under load, even in high application temperatures. The materials used may not slide away under pressure. This applies in particular when so-called columns with multiple disc cells are braced with one clamping device. Never install columns horizontally into the control cabinet. Shearing forces may result which can fracture the silicon wafer in the disc cell.

Mounting clamp for 50kN with leaf spring, indicator, pressure pad, isolator, semiconductor and heat sink

The contact pressure must be applied across the whole surface of the disc cell. It may under no circumstances be applied eccentrically or even at individual points. Usage of a pressure distributor is a sensible option here – especially for large disc cells.

The contact pressure must be applied centrically onto the disc cell, even if the tension bolts are not tightened evenly (within limits). In addition to the pressure distributor already mentioned, the use of an additional compensator is a sensible option, especially when using larger disc cells, to effectively prevent uneven pressure distribution. Uneven tightening of the tension bolts must be avoided. Otherwise, this poses the risk of the silicon wafer breaking.

The contact pressure must be capable of being applied reliably allowing for all the tolerance values of the materials used in the clamping assembly.

The materials used in the clamping assembly, especially pressure distributors, insulators, thrust bearings and the contact surfaces of the heat sinks must be plane-parallel.

The clamping system must be capable of applying the required contact pressures in a reproducible manner.

The clamping system should ideally have a pressure indicator. This simplifies the replacement of defective power semiconductors on site considerably because the contact pressure adjustment can be reproduced again and again without using special tools.

Under-determined (e.g. only one tension bolt) and over-determined (e.g. four tension bolts) clamping systems must not be used.

Note the length of the centering pins. They must be shorter than the stud hole in the disc cell is deep.

Alternately tighten the nuts of the tension bolts maximum of ¼ turn. Ensure the tension bolts and nuts have adequate tensile strength. Use a fine pitch thread if required (recommended for disc cells > 3”).

The heat sinks used in the clamping assembly must have exactly defined evennesses and roughness depths (approx. 10 μm) for the contact surfaces to the disc cell. The use of a (ultra)-thin layer of heat-conductive paste is recommended (please also refer to the next section).

Mounting clamp schematic right and falsem

Heat-conductive paste, a never ending story

It must be noted here that the expression heat-conductive paste defines an incorrect concept - this is because usage has its downsides. Applying too much (“a lot helps a lot”) considerably increases the thermal resistance between power semiconductor and heat sinks. Applying too little has the same effect. Both can result in thermal overload as a result of poor heat dissipation. This fundamentally applies to both the discrete and module design of power semiconductors.

The ideal heat transfer between power semiconductor and cooling unit would be a best possible adhesively joined, flat, metallic transition with a low roughness depth but without air inclusion. Such junction regions are not realisable in practise due to cost considerations. For example, many modules with solder-contacted chips exhibit convex module base plates – other design technologies such as pressure- contacted modules exhibit convex/concave-shaped base plates caused by the high tensile and pressure forces developed by the internal clamping device. The heat sinks themselves are also not perfectly even.

This applies analogously for discrete power semiconductors in screwed and flat base housings, as well as disc cells and plastic moulded type power semiconductors.

So attaching power semiconductors to heat sinks inevitably results in air inclusion. Air has a heat conductance up to 200 times lower than a good heat-conductive paste. Applying heat-conductive paste should therefore prevent air inclusion and ensure that the value for thermal

transfer resistance from power semiconductor housing to cooling unit, specified in the data sheet, is attained.

The correct and reproducible application of heat-conductive paste therefore takes on fundamental significance.

When using modules and discrete power semiconductors, different heat-conductive pastes are deployed. For discrete power semiconductors, heat dissipation and current are routed over the same interface. Not suitable here are heat-conductive pastes optimised for power semiconductor modules with electrically insulated base plate.

Suitable for discrete power semiconductors are heat-conductive pastes such as Bechem Rhus or for modules, e.g. DC340 (Dow Corning) or P12 (Wacker).

Note that all pastes must be free of impurities and foreign particles. Old thickened or clumped heat-conductive pastes may not be used.

Heat-conductive pastes not completely used up must be disposed of daily.

Applying heat-conductive paste is a science in itself. It can be applied to the power semiconductor itself or to the heat sink. The best layer thicknesses are between 30 µm and 100 µm depending on the filler materials used in the heat-conductive pastes (e.g. graphite, silver, zinc oxide). Which method is used for applying heat-conductive paste essentially depends on the number of power semiconductors to be assembled. It is important for all methods that the application is reproducible so as to guarantee the same thermal transition resistances from the housing of the power semiconductor to the cooling unit.

Rolling on the heat-conductive paste:

This method is recommended for assembly of smaller to mid-sized quantities. To prevent too high a level of fluctuation in layer thickness, this process should only be performed by specially trained and experienced employees. A rubber roller is used to apply the heat-conductive paste to either the power semiconductor or the heat sink.

Manual application with screen-print or templates:

This method is suitable for medium to high quantities. The raster of the screen/template broadly eliminates the risk of inhomogeneous paste application and significantly improves reproducibility of the application.

Automated application using a press:

When assembling high volumes, it is certainly wise to commit to the costs accompanying such an investment. Process fluctuations are broadly eliminated, manifesting itself in very good reproducibility of the paste layer thickness.

Whichever method is used, it makes sense to check whether the layer thickness of the heat-conductive pastes applied is correct. For this, heat-conductive paste is applied to the power semiconductor as described above. The power semiconductor is mounted onto the heat sink with the nominal tightening torque or contact force. The entire system should be allowed to settle for several hours and, if possible, be subjected to several temperature changes (e.g. 25°K/100°K). Afterwards the power semiconductor is removed carefully from the cooling unit and the resulting print impression of the heat-conductive paste assessed. If non-moistened contact areas can be seen on the power semiconductor, the application was too thin. If the whole of the contact area is moistened and the metal is shimmering through the heat-conductive paste, the application is correct. If the contact surface of the power semiconductor no longer shimmers through the heat-conductive paste, the application is too thick.

The thermal design influences the overall size

Heat-conductive paste applied with a screen-print

Applying different heat-conductive paste layer thicknesses (starting at, for example, 50 µm in 10 µm increments) is the best way to reach the optimum application. Layer thicknesses are best determined with "test combs".

Data sheet values are spotlights

Not every value specified in the data sheet is explained and discussed at this point. Here it is more about the scenario in which power semiconductors suddenly no longer work or are even defective when operating in the same environment and application.

A manufacturer’s specification is the basis for every power semiconductor data sheet. This specification may be a mirror image of the data sheet. However, it may also be the case that, for political or safety reasons, the values in the specification have a somewhat stricter definition than in the data sheet. These are the “hidden reserves” required by the power semiconductor to be able to demonstrate an acceptable life expectancy.

These are not disclosed to users — the specifications in the data sheet apply for them. It must also be noted that the specifications in the data sheet only apply under the conditions stated therein. If these conditions are different in the application, the data sheet specifications must be interpreted accordingly, and the reliability of operating points must be supported by calculation using generally accepted calculation methods.

Misinterpretation may result in the user operating power semiconductors, deliberately or unwittingly, in operational windows which are possible given the physical properties of the power semiconductor, but which are no longer substantiated by the data sheet.

Within a batch of power semiconductors slightly different values occur for every parameter specified, which may be grouped closely together under certain circumstances but can also be represented in the form of a distribution curve. Records over multiple batches show the entire breadth of the distribution of parameter values caused by the production process.

Heat-conductive paste applied on an IGBT module

If the design is within such a grey zone and the manufacturer changes or optimises the process it may occur that the semiconductors of the next delivery conform to all the specification values and data sheet values but still will not work in the application or even become defective. The same applies when a competitive product is to be used because of delivery difficulties.

In this context, the ignition current (Igt) of a thyristor is to serve as the typical and ever recurring example. The ignition current specified in the data sheet is a declaration stipulating simply that, under the conditions specified, all manufactured thyristors must ignite (generally at room temperature and at an anode-cathode voltage of 6 V and a minimum ignition pulse duration of 20 µs). This means that the majority of the thyristors can be ignited with ignition currents lying well below the specifications in the data sheet. The basic conditions also show that such an ignition current has little to do with application conditions.

How a thyristor needs to be ignited under application conditions is specified under di/dtcr. Usually required here is the fivefold of the Igt value specified with an ignition current rise rate of 1A/µs and longer ignition pulse widths/post-ignition pulses.

If, for cost reasons (weak ignition pulse levels are more cost-effective), a user assumes that all thyristors can be ignited well below the Igt threshold, the following problems automatically arise:

Reliable ignition at low temperatures is not guaranteed: Malfunctions may occur.

Reliable ignition with load current rises typical for the application is not guaranteed: Long-term failures with so-called di/dt errors may occur. Subsequently increasing the ignition current with the existing ignition board is no longer possible in most cases.

Following process changes, the “new” thyristor may no longer be capable of being ignited although the data sheet values are maintained.

The use of thyristors from alternative sources may not be possible although they have the same, or even lower, Igt values.

The situation is similar when the application requires that power semiconductors are operated in series or parallel connection. Here, characteristics of the power semiconductor have to be used which are not substantiated by the data sheet by default.

As long as the power semiconductors come from one batch, the variance of individual parameters required for the particular application may be so low that series or parallel connection works. When, however, power semiconductors from different batches are used together, the risk is extraordinarily high that failures will occur in the application as a result of using power semiconductor characteristics not supported by the data sheet.

Thermal design determines device dimensions

Arguably the most important issue in developing power electronic stacks is thermal design because this essentially determines the physical size of the system. By their very nature, the load currents required in the application generate thermal power losses in the power semiconductor that need to be dissipated via the heat sinks in the form of heat loss. In principle, heat sinks may be self-ventilated, separately ventilated or liquid-cooled.

The load currents occurring must of course be known so as to be able to accurately determine losses, and hence the size of the cooling unit and type of cooling. Overload conditions in regard to magnitude and time must be known just as much as load values for undervoltage operation.

It is equally important to know how and under which operational conditions the power electronic devices are deployed. Power electronic stacks which are subjected to high, rapid step changes in load must have an altogether different thermal design compared to power electronic devices running continually with minor load changes for days on end. The mechanic design of the selected power semiconductor and its associated long-term operational behaviour play a key role here.

In combination with the circumstances given above, it is sensible to ensure that power semiconductors from different manufacturers can also be deployed as an alternative to avoid single source situations.

All of these facts must be taken into consideration in the final thermal design. The thermal design may well be inadequate if load requirements are not specified correctly, operating conditions are not assessed correctly or if power semiconductors are not selected properly.

Quite often, designs can be found, which have to make use of the hidden reserves to cope with critical load conditions or the users hope that not all worst case scenarios will coincide. The power semiconductor is then operated in the critical grey areas already described above.

Subsequent optimisation of these kinds of designs is usually associated with major overhead and is often not possible for mechanical reasons, often resulting in exotic attempts to rectify the problem - such as gilding the contact surfaces of the power semiconductors used.

Long-term properties and reliability - in-built reserves make the difference

The belief that power semiconductors are non-wearing and non-ageing is not correct in this sense. For example, the silicon integrated in the power semiconductor reacts to different voltage loads. Therefore, a permanently applied DC voltage clearly stresses the silicon more than an AC voltage of the same magnitude. Also, given the highenergy cosmic radiation, the risk of damage to the silicon is greater the more the silicon is loaded in terms of voltage. With appropriate reserves in the voltage design, these risks are easily controlled and minimised provided they are taken into consideration in the development phase. Power semiconductor manufacturers regularly conduct reliability tests in the form of voltage stress tests to verify the longterm voltage stability of power semiconductors. For this purpose, DC or AC voltages are applied to the power semiconductors over specified time periods and at defined temperatures. The leackage current is also logged in parallel and should show values which are as stable as possible.

As described previously, power semiconductors are made up of a mix of materials. This mix has already been described for the disc cells. For modules, the base is often a copper base plate and the silicon sits on copper-coated insulator ceramic. A differentiation is made between solder-contacted and pressure-contacted module technologies. For IGBT modules, there is an additional technological weak point: chip-bond contacting.

If this mix of materials is heated cyclically with alternate loading, the different materials will expand differently. The junction areas are stressed, the thermal transition resistances start to rise and the transfer reserves and the reserves in blocking behaviour are slowly wasted. Then, sure enough, the power semiconductor fails as a result of ageing.

Different life expectancies can be assumed for different design technologies.

Over the same temperature range, several tens of thousands of such load cycles can be expected for TO247 and isotope housings, for IGBT modules, several hundred thousand depending on design and several millions for disc parts.

Power semiconductor manufacturers verify and document this load cycle stability with appropriate reliability testing.

This information is of enormous importance when designing power electronic stacks. Whilst a fan drive can have a life expectancy of years for a specific load and the resulting defined temperature range, the same drive used as a lift drive operating under the same loads will have a life expectancy of just a few weeks.

If the application demands these frequent load cycles and the power rating may not be reduced, the temperature range must be reduced to attain the prolonged service life required. This can only be achieved with over-dimensioning of the power semiconductor compared to the power rating required. This can be realised only if there is sufficient room for improved cooling and larger IGBT modules.

Actuation of bipolar power semiconductors - “power” is everything!

Bipolar power semiconductors are controlled by current. This requires a powerful trigger circuit to be able to provide the required ignition current. The risks of inadequate ignition are addressed in the previous section.

In practise, there are many drives with poor design that do not meet the minimum requirements. A supply voltage that is too low is often selected (12 V is borderline here). The same applies for the power supply provided.

This narrows down any potentially necessary optimisation options or for very unfortunate scenarios averts the use of possible alternatives in the event of supply bottlenecks because they may require a higher ignition current.

With a supply voltage of e.g. 24 V, a powerful power supply protected against short-circuit current and an ignition pulse transformer capable of transferring strong ignition pulses with ignition times of 250 µs with a repetition rate of approx. 2 kHz, the design is on the safe side and all of the problems described above are averted.

Activating Bi-Mos power semiconductors – control power desired!

Bi-Mos power semiconductors are voltage-controlled. Applying a positive control voltage of 15 V turns it on; removing the control voltage switches it off. Activation is very simple and requires practically no power. This is more or less how it is portrayed in technical literature. Such an activation design must of course not cost much, something reflected in many driver board designs.

In reality, the design of a driver board is the technical crux in the overall design of an inverter, is very complex and anything but simple. No other power semiconductors reflect design errors in the driver board so strongly into the overall design than IGBTs.

There are quite a lot of driver boards where only 12 to 13V of the control voltage reach the gate of the IGBT at rated supply voltage or the power supply units become hot at the required switching frequency because large IGBTs in particular require significant levels of power or for which it is not possible to momentarily deliver relatively high current peaks (a few A to 10 A depending on application) to the gate for specific adjustments and the minimisation of switching losses. Such driver board designs do not allow anymore leeway in order to take corrective action in view of switching loss optimisation, controlling overcurrent and short-circuit current cut-off.

The only solution here is a complete redesign.

This redesign, which is tailored to the IGBT size selected, should be as follows:

 • Reliable gate voltage supply with +/- 15 V, even for supply undervoltage
• Design of the power supply unit in line with power rating
• High pulse current capability for the possibility of hard switching loss optimised gate control
• High dv/dt immunity
• Low coupling capacity
• General-purpose usage for IGBTs of the same size, but from different suppliers.

 

 

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