Categorized | Drivers, Power Devices


Posted on 08 February 2020

Driver Circuit Structures








Figure 1 below shows the basic structure of a high performance driver circuit for a MOSFET or IGBT bridge arm which, in addition to the basic gate driver function, includes TOP/BOTTOM interlock, protection and monitoring functions, as well as pulse shapers.

The driver depicted features TOP and BOTTOM switches of the central logic and control units (microprocessor, DSP, FPGA) separated by potential isolation for control signals, driving energy, as well as state and error feedback signals. In less complex driver circuits such as used in low cost applications, these potential isolations may either be combined (common energy and signal transmission) or have no electrical isolation (e.g. bootstrap circuits for TOP voltage supply; level shifter for signal transmission to the TOP switch). Low voltage switches, especially those used in applications with low converter voltages or low side choppers (only BOTTOM switch is active), require a very simple driver structure only  since individual driver functions can be easily implemented or even dispensed with (e.g. interlock and dead time functions).

Block diagram of a high-performance IGBT bridge arm driver circuit

Figure 1. Block diagram of a high-performance IGBT bridge arm driver circuit with TOP/BOTTOM interlock, protection, and monitoring functions

The gate unit is the core part of the driver circuit and consists of (mainly) primary side time control stages for delay, interlock, and minimum on and off times, potential isolation (with pulse shapers, if necessary) and a generator for positive/negative gate control voltage. Overvoltage protection, sometimes also combined with active clamping for vDS or vCE, may be connected directly at the power transistor gate.

Figure 2 shows the principle behind a driver output stage for positive and negative gate control voltage (designed for IGBT with negative gate-emitter voltage).

Besides the complementary stage with low power MOSFETs (or bipolar transistors), totem pole drivers (push-pull output stage) with MOSFETs or bipolar transistors and emitter followers are also commonly used.

Driver output stage for gate control voltage turn-on and turn-off

Figure 2. Driver output stage for gate control voltage turn-on and turn-off

The gate resistance RG in Figure 2 is split up into two resistances RGon and RGoff for turn-on and turn-off, respectively. Thus, cross current conducted from VGG+ to VGG-, which is almost inevitably generated during switching of the driver MOSFET, can be limited. The main advantage offered by this solution, however, is that the turn-on and turn-off processes can be optimized individually with regard to all dynamic parameters and the switch is fully controllable in the event of malfunction or error. If only one output is available for RG, this function can also be maintained by equivalent circuits such as parallelling RGon and RGoff with the diodes connected in series to the resistors arranged such that the cathode is directed towards the IGBT gate for RGon and the anode is directed towards the IGBT gate for RGoff.

The gate-emitter resistance RGE (10... 100 kW) should not be omitted in any application, since it prevents unintentional charging of the gate capacitance even under driver operating conditions with highly resistive output levels (switching, off-state, and driver supply voltage breakdown). This resistor must be positioned next to the transistor control terminals.

The low-inductive capacitors C serve as a buffer for VGG+ and VGG- near the driver output and - in connection with the sufficiently low-resistive driver circuit - provide a minimum dynamic internal driver resistance. The capacitors provide the gate peak currents required for fast switching. They are also important in the process of passive gate voltage clamping of the driver supply voltages (gate overvoltage limitation) by means of Schottky diodes.

In addition, the following aspects are to be borne in mind for the driver output stage layout:

  • minimum parasitic inductances in the gate circuit, e.g. short (<< 10 cm), twisted connection lines between driver and gate/driver and emitter (source); minimum circuit area in accordance with Figure 2
  • elimination of load current feedback to the gate voltage caused by the parasitic emitter/source inductance in the power module
  • avoidance of ground loops
  • avoidance of transformatory and capacitive coupling between gate and collector circuit (oscillation tendency)

For low-pass filters, pulse shapers and pulse-width-triggered flip-flops integrated into the signal transmission paths for interference suppression, delay times must be able to accommodate the permissible minimum pulse duration and the necessary response times in the event of malfunction/error.


For more information, please read:

Driver Circuits

Gate Current and Gate Voltage Characteristics for Drivers

Connection of Gate Drivers to IGBT and Controller

IGBT Driver Calculation


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