Posted on 18 June 2019

Dual Common Drain Trench Power MOSFETs

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Supplied in Wafer Level Chip Scale Packages for Next Generation Mobile Applications

As consumer expectation for long battery life and high processing capability rise, cellular phones and tablets are placing increasing demands on charging and battery protection power MOSFETs. A common-drain back-to-back power MOSFET in the battery pack protection circuit module (PCM) allows control of the charging/discharging as well as protection from short-circuit, over-voltage, under-voltage and similar battery fault conditions that can damage the appliance. Very low in-line voltage drop of this power device helps to extend the operating time of the downstream circuitry and reduces the power loss while transferring energy from the battery to other circuits.

By Ritu Sodhi and Sukhendu Deb Roy, Fairchild Semiconductor, India and Ihsiu Ho, Chung-Lin Wu, and Steve Sapp, Fairchild Semiconductor, USA


For the appliance designer, a compact size with very low on-state resistance enables a smaller circuit board for increased internal volume, which in turn allows a larger battery, increased functionality, or a smaller device. A common-drain power MOSFET enables the independent regulation of bi-directional current flow through the device that the battery pack PCM circuit requires. The common-drain configuration also lends itself well to the basic device structure of the common power MOSFET device that uses the backside of the chip to connect to the drain of the transistor. Arranging two independent source and gate connections on the top surface completes the desired power control device.

Trench power MOSFETs have been the devices of choice for low voltage applications. The greatest benefit of the trench MOSFET technology is that it enables a much higher channel width when compared to a planar VDMOS structure [3, 4]. More importantly, because of increased channel width, the channel resistance is reduced significantly. With increased channel width density in this device structure, the channel resistance is significantly reduced, and the drift resistance becomes more prominent even for these low voltage devices. The charge balance concept, originally developed for high voltage devices, has become an attractive option to reduce the drift resistance, even for low voltage MOSFETs [5, 6].  The manufacturing of charge balance devices can be more complicated and expensive. The device technology discussed here combines high channel width density with a charge balance feature using shielded gate trench architecture to provide exceptionally low on-resistance. Figure 1 shows the shielded gate device structure, where an additional shield electrode has been included below the gate electrode and includes a thicker insulating layer than the gate dielectric. The shield electrode and gate electrode are separated by an inter-electrode dielectric (IED). As the gate electrode is isolated from the drain electrode by the shield electrode, considerable reduction in gate-to-drain capacitance (Cgd) can be achieved. The shield electrode plays an important role in optimizing the device performance, whether it is connected to the source or the gate electrode. Both of these approaches allow an increase in the doping concentration of the drift region due to field plate effect of the shield electrode. Increasing the depth of the shield electrode into the drift region improves the charge balance effect and provides higher than parallel plane breakdown for a given drift region concentration. The increased breakdown can then be leveraged for reducing the R(DS)(ON). The new optimized devices offer over 50 percent reduction in specific on-resistance, as compared to previous conventional trench technology. Figure 2 shows the figure of merit comparison between this technology and earlier device technology, as well as to other competitive solutions used in this application. Table I shows the typical electrical parameters of a 20V, N-channel device, comparing simulated and measured data. The results show that the two sets of parameters are within 10 percent of each other, showing a good correlation to the simulations.

Device cross-section and simulated structure for the latest generation low voltage  MOSFET

Figure of Merit Comparison

Typical electrical parameters of the optimized device – simulated vs. measured data

For the dual common-drain architecture, the major components of source-source on-resistance are the main device resistance, the substrate and back metal resistance, primarily due to lateral current flow from one source to the other. The advanced MOSFET technology used in this device, to reduce on-resistance of channel and drift resistance components, causes the substrate and back metal resistance contribution to become substantial. This resistance can be reduced by one or all of the following: (i) thinner substrate and thicker back metal, (ii) lower resistivity back metal, and/or (iii) reduced distance from the first to the second source areas. However, each of these approaches has its own set of benefits and challenges. Wafer level chip scale packaging (WL-CSP) has received much interest lately since it offers solutions to these problems. WL-CSP is widely used in portable electronic equipment like cellular phones because of their smaller size and low parasitic resistance and inductance. The low capacitance of the WL-CSP design has better applicability to high-frequency devices than traditional lead-type packages like thin small outline package (TSOP).

Fairchild Semiconductor’s power MOSFET WL-CSP has been carefully optimized for the mobile power application. Figure 3 shows the profile of a typical WL-CSP product housing a dual common-drain MOSFET. Extensive simulations have contributed to determining the optimum layout of the WL-CSP design and the thickness of back metal to minimize resistance waste in the substrate of the device. Figure 4 shows the simulation structure. The simulations use the specific on-resistance of the MOSFET unit cell, along with other parameters from the device, to compute the total source-source on-resistance (Figure 5). The layout of the solder balls is optimized for lowest Rss(on) and also for ease of use in the specific application. A typical process flow for these WL-CSP devices includes the following steps. A polymeric layer is first deposited on the top passivation of the incoming wafer for stress buffering. After this, the under bump metallization (UBM) is deposited on the pads for the subsequent lead-free solder bumping process. The 0.5 mm or 0.65 mm layout pitch allows for direct surface mounting of the die on a standard PCB, leveraging the existing board assembly infrastructure without requiring the more expensive high density boards. This is followed by ball drop and reflow processing, all before the devices go through final testing (done in wafer form).

Package outline and schematic of the Dual Common Drain MOSFET in a WL-CSP

WL-CSP device as simulated using ANSYS® software

Simulated product Rss(on) vs. specific on-resistance of the MOSFET device

One of the critical aspects of a new package is its reliability. For our new products, the WL-CSP 1.0 x 1.0mm, 4 ball 0.5mm pitch was tested in the board level temperature cycling, drop and cyclic bend test. Figure 6 shows the test setup and profile used for these tests. These tests are intended to assess board level reliability of the WLCSP package. The test follows established industry standard and best practices which intend to simulate stress conditions during board mounting and in field application. The three tests conducted for these CSP devices included temperature cycling, drop test and cyclic blend. The temperature cycling test is intended to provide information on the wear out performance of the solder joint attachment of surface mount devices to circuit boards where cyclic stresses due to CTE mismatches from thermal loading may result in fatigue-related failures. The drop test is intended to determine the ability of the mounted component to withstand moderately severe shocks such as a result of sudden applied force or sudden change in motion produced by handling, transportation, normal field operation, accidental misuse or drop of the product. The cyclic bend test is intended to characterize the fracture strength of the board level interconnects due to flexural loading that is cyclic or reiterative in nature.

Temperature profile used for temperature cycling test

Test setup and board placement for the drop test

Mounting scheme for the cyclic bend test

The products were subjected to all these tests using the conditions listed in Table II. All parts passed the tests and no solder joint failures were observed. There was just one failure in the drop test and that was also not related to the device, but due a crack in the Cu trace as seen in Figure 7. All reliability criteria were met and the technology has been successfully released to market.

Test conditions and test results for the three board level reliability tests

Failure analysis of the drop test fail, showing that there is no anomaly with the device

With the advancements in power MOSFET technology that provide reduced resistance silicon, like the latest generation PowerTrenchR technology from Fairchild Semiconductor, and the optimized WL-CSP technology, we are able to provide ultra small footprint solutions. The ultra low Rss(on) of these devices helps in minimizing the total power loss, which in turn prolongs battery life and usage time.



1) M. Topper et al, "Wafer-level chip size package (WL-CSP)", IEEE Trans. on Adv. Packaging, Vol. 23, No. 2, pp. 233-238, May 2000.
2) P. Garrou, "Wafer level chip scale packaging (WLCSP): an overview", IEEE Trans. on Adv. Packaging, Vol. 23, No. 2, pp. 198-205, May 2000.
3) D. Ueda, H. Takagi and Kano, G. "A new vertical power MOSFET structure with extremely reduced on-resistance, IEEE Transactions on Electron Devices," Vol 32, No. 1, pp. 2-6, 1985.
4) R. Sodhi et al, “High-density ultra-low Rdson 30 volt N-channel trench FETs for DC/DC converter applications,” Proceedings of the 11th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 1999.
5) G. Deboy et al,“ A new generation of high voltage MOSFETs breaks the limit line of silicon”, pp. 683- 685, Proceedings IEEE Electron Device Meeting, 1998.
6) R. Sodhi et al, “High cell-density, shielded-gate power MOSFET for improved DC-DC converter efficiency”, PCIM-Europe, 2010.



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