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Posted on 21 December 2019

Electromagnetic Interference in Converters (EMI)

 

 

 

 

 

 

 

The processes that take place in a converter system will always produce unwelcome electromagnetic interference due to the switching of the power semiconductors, on the one hand (Figure 1), and welcome energy transmission with corresponding signal processing, on the other hand.

Energy processes in converters

Figure 1. Energy processes in converters

These processes can be divided up into high energy processes, which may cause interference in the mains and the load within a frequency range between fundamental frequency and about 9 kHz, and low energy processes above 9 kHz up to about 30 MHz, where noise emission and, consequently, non-conducted current flow will start to be propagated. In the low frequency range, these effects are called converter mains feedback, which are normally characterised by discrete harmonic current oscillations up to about 2 kHz. At higher frequencies, these oscillations are called radio interference voltages or radio interference and are given as interference voltage spectra in dB/mV for reasons of selective measurement. Terms such as zero current, leakage current, or asymmetrical interference voltage only differ with respect to their assignment to different frequency ranges and with regards to the frequency dependency of the switching parameters. Since this frequency dependency is continuous, as is the transition to radio interference, the frequency transition range is inevitably very wide.

Causes of interference currents

Equivalent commutation circuit with noise propagation paths

Figure 2. Equivalent commutation circuit with noise propagation paths

In the case of inductive commutation, switch S1 will switch over to conducting switch S2. In a hard switching process (LK = LKmin , CK = CKmin ), the current is initially commutated with a di/dt that is given by the semiconductor characteristics of switch 1. Commutation is finalised by the reverse recovery di/dt of switch 2, which determines voltage commutation and, consequently, dv/dt along with the current carrying inductance and the effective capacitances CK . The effective capacitances comprise all capacitances CΣ which are effective towards the neutral potential. In addition to the impedances of the commutation voltage connections to the neutral potential, parallel impedances of the commutation capacitances will become effective. At the beginning of the commutation process, the di/dt of switch 1 will cause a symmetrical current flow idm (differential mode) within the commutation voltage capacitance and the parallel network 1. The dv/dt at the end of the commutation process caused by the reverse recovery di/dt of switch 2 and the inductance L, which serves as a supply current, conducts the currents icm (common mode) asymmetrically via the ground line through the parallel lines to the commutation capacitances CK .

Transition to soft turn-on induced by an increase in LK reduces the di/dt, thus minimizing symmetrical current interference. At the same time, the increased inductances LK are effective in the asymmetrical interference current circuit. At the beginning of the commutation process, dv/dt is determined by the switching characteristics of S1. The voltage leap at the end of the commutation process is determined by the reverse recovery current behaviour of switch S2. Transition to soft switching in ZCS (Zero Current Switching) mode reduces symmetrical current interference and changes the frequency range of asymmetrical currents, without reducing them considerably.

The capacitive commutation process is begun by active turn-off of switch S1. In hard switching processes (CK = CKmin ), the asymmetrical interference current is determined by the impedances towards the neutral potential which are effective parallel to the commutation capacitances, and by the semiconductor characteristics of switch S1. The current commutation which is triggered after voltage commutation, and, consequently, the symmetrical interference current is determined by the turn-off behaviour of S1 and the turn-on behaviour of S2.

An increase in CK calls for the use of a zero voltage switch with soft turn-off behaviour. The turn-off process starts with the first stage of current commutation at a di/dt determined by switch S1 at a reduced voltage. The delayed dv/dt will reduce the asymmetrical currents during voltage commutation. Passive turn-on of S2 determines the di/dt during the second stage of current commutation. Asymmetrical current interference will be reduced by soft switching in ZVS (Zero Voltage Switching) mode without changing symmetrical currents noticeably. Nevertheless, the increased capacitances CK will diminish the symmetrical interference current in network 1 in relation to the capacitive current divider. Soft switching converter circuits (resonant, quasi-resonant) with turn-on or turn-off phase shift control will reduce asymmetrical and symmetrical interference currents when using zero voltage switches or zero current switches. In converter circuits with auxiliary commutation arms, where ZVS and ZCS are switched alternately, interference currents will not be reduced considerably in comparison to hard switching circuits, since both high di/dt and dv/dt are involved in the total system within one switching cycle.

Propagation paths

In order to detect conducted radio interference voltages, selective measurements of voltage fluctuations at the mains connections for inverter to ground are taken. The potential fluctuations refer to a defined point of ground, which is determined in standard measurements by connecting a line impedance stabilization network. Regarding symmetrical and asymmetrical interference currents within the frequency range of EMI, all simple low frequency switching elements are equipped with additional inductances, resistances, and capacitances, which will render a clearer simulation of their frequency dependency.

Figure 3 shows an example of a simple step-down converter circuit, where network 1 is represented by the line impedance stabilisation network (LISN) and network 2 by the applied load in contrast to Figure 2.

EMI equivalent circuit of a step-down converter

Figure 3. EMI equivalent circuit of a step-down converter

The module simulates switches S1 and S2, including the commutation circuit inductances and capacitances. The aforementioned origins of interference currents are illustrated in a simplified way, namely as current source IS for symmetrical interference currents and as voltage source VS causing asymmetrical interference currents. In both sources, the measured semiconductor characteristics are included as a function of time (Figure 4).

Typical voltage and current characteristics of an IGBT switch

Figure 4. Typical voltage and current characteristics of an IGBT switch (top characteristic in V, bottom in A)

Figure 5 shows simulated results with the example taken from the model shown in Figure 3; these results agree well with the actual measurements taken.

Simulation results for a 1200 V - 50 A NPT IGBT dual module

Figure 5. Simulation results for a 1200 V / 50 A NPT IGBT dual module; Operation parameters: DC link voltage VZ = 450 V; Load current = 20 A; Pulse frequency = 5 kHz

Other causes of electromagnetic interference (EMI)

Component related oscillation effects are identified as reasons for electromagnetic interference beyond the circuit related effects (parasitic frequencies in the range of 100 Hz - 30 MHz), which can be summarized as follows:

 LC oscillations

(1) Oscillations that occur when switching individual power semiconductors (IGBT, MOSFET, diode)

Cause: excitation of resonant circuits consisting of the non-linear intrinsic semiconductor capacitances and the parasitic circuit environment (L,C)

Interference frequency range: 10 - 100 MHz

Counter-measure: circuit layout optimization, reduction of switching speed, limitation by external circuits

(2) Oscillations in paralleled or series-connected IGBT / MOSFET or diode chips in modules or press-packs

Cause: variations in parameter tolerances among the chips; asymmetries in the parallel / series circuit layout (also applicable to series or parallel connection of discrete components and modules)

Interference frequency range: 10 - 30 MHz

Counter-measure: circuit layout optimization (balancing), use of suitable gate series resistors, chip optimization, reduction of switching speed, limitation by external circuits.

 Oscillations during charge carrier transit time

(1) PETT oscillations ( Plasma Extraction Transit Time)

Cause: occur in the tail current phase of the turn-off process of bipolar components (IGBT, soft recovery diode); the space charge zone collides with a pile of (free) charge carriers which form the tail current; PETT oscillations occur in the form of radiated electromagnetic interference

Interference frequency range: 200 - 800 MHz

Counter-measure: avoid LC circuits with resonant frequencies in the PETT oscillation range in the module design

(2) IMPATT oscillations ( Impact Ionization ( Avalanche) Transit Time)

Cause: dynamic process during diode turn-off; the electrical field encounters the residual pile of (free) charge carriers; the diode changes dynamically to avalanche state (electron impact ionisation), IMPATT oscillations occur in the form high energy radiated electromagnetic interference

Interference frequency range: 200 - 900 MHz

Counter-measure: optimization of chip design

EMI suppression measures

Conventional conducted interference suppression is based on the use of customized filters or standard filter topologies which are attached to the mains and load side of the device. According to the set limit characteristics for a certain type of device or application (defined in terms of radiation and immunity by national and international standards for conducted and radiated EMI), various filters are used by means of line impedance stabilization networks and standardized test assemblies, until the limit values are complied with in all frequency ranges.

In this largely empirical approach, the filters used are often both complex and costly. Whether the use of a simulation tool for optimizing the overall EMC (Electromagnetic Compatibility) system layout makes sense or not should be verified individually for each application since model generation and the parameterization processes involved are rather time consuming. Basically, it is effective to design and construct a circuit that takes into account the effects of electromagnetic interference and the optimization of propagation paths with respect to their origins and available measuring points at the beginning of the development processes. Optimization means either producing high resistance propagation paths for interference currents by applying selective blocking circuits or creating low resistance short circuit paths for interference currents by using selective suction filter circuits. The selected measures are explained below with regard to Figure 2.

Symmetrical interference current circuits will be closed via the capacitance of the commutation voltage source. Ideal capacitance connected to switches 1 and 2 without the influence of any line impedances would be required for the creation of a short circuit path for interference currents. Measurable radio interference voltages will then be generated via the capacitive voltage ripple, effecting current flow over the parallel effective circuits. Therefore, all measures that may be taken to reduce symmetrical interference currents aim at the positioning of suitably connected suction filter circuits parallel to the connection lines of the commutation voltage. The closer the ideal capacitances (low intrinsic and ohmic inductance) and active suction filter circuits can be connected to the switch connection points, the less effort is involved for EMI suppression.

Essentially, asymmetrical interference currents are propagated via the ground line. In the context of interference suppression, extremely high resistance impedances seem to be important at all switching points with steep potential increases versus ground potential, limiting the jumping potential to the nonavoidable switch connection points at the same time. In the example of the equivalent circuit in Figure 2, interference suppression was initially implemented by using reduced parasitic coupling capacitances of the potential isolating components of the drivers and capacitances effective via the module base plate and the heatsink. If the drivers are not supplied with switching information or auxiliary energy by the neutral potential, displacement currents are not conducted via the earth line, i.e. the circuit is closed inside the device. There will be no flow of asymmetrical interference currents. Interference currents propagating across the base plate can be reduced by optimizing the module layout and materials. EMI suppression measures implemented close to the power semiconductor chips may considerably reduce interference currents, as shown in Figure 6 on the example of a modified IGBT module.

Interference spectra of a standard IGBT module compared to an EMI-optimised IGBT module

Figure 6. Interference spectra of a standard IGBT module compared to an EMI optimized IGBT module; Operation parameters: DC link voltage = 450 V; Load current = 20 A; Pulse frequency = 5 kHz

The connection to network 2 via the choke coil depicted in Figure 2 remains unaffected. A reduction in the coupling capacitance can only be achieved by reducing the connection line to a minimum. Ideally, an L/C filter should be connected directly to the the jumping potential. Thanks to the filter inductance, potential jumps are attenuated to such an extent that all other coupling capacitances in network 2 will be unable to noticeably contribute to the asymmetrical interference current. Should network 2 serve as the mains supply point where the LISN standard measurement takes place, this step is an absolute must, i.e. the L/C filter must be part of the EMI filter. In addition to the use of EMI filters, additional measures with respect to earthing and shielding are performed in practice in order to improve EMI behaviour.

 

For more information, please read:

Fuse Placement in Typical Converter Circuits

Four Types of Switching Processes

Gate Resistors – Principles and Applications

Influence of parameter distribution and mechanical construction on switching behaviour of parallel IGBT

 

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