Posted on 06 November 2019

Extending the MOSFET Gate Drive Conductors

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Using a Dual Stripline PCB Layout Configuration

In many applications there will be a need to place one or more rails in a Power XR application at some distance from the controller. This article will introduce and examine from both a theoretical and practical standpoint a layout design technique that will allow the MOSFETs to be as much as 5 inches from the driver.

By Ron Berthiaume, Exar

The Exar XRP77XX series family integrates internal gate drivers for all 4 PWM channels. These drivers are optimized to drive both high-side and low side MOSFETs for synchronous rectification operation.

Normally these drivers are required to be close to the MOSFETs they are driving due to their high current and high speed rise and fall times.


When the MOSFETs are moved away from the driver (more than 1 inch) the parasitic capacitance and inductance of the layout can become dominate resulting in inadequate performance of the power system. In order to eliminate these parasitic issues, this article describes a layout approach that allows the power stage to be as much as 5 inches from the driver and still work as expected. The basis of the operating theory is that the drive to the MOSFETs is a pulse of current and that if one views the drive conductors as a pulse transmission line with a capacitive termination (gate and Miller capacitance) then the parasitics can be minimized.

A Dual Stripline (also called a broadside coupled stripline) was chosen in order to have the magnetic field produced from the current pulse that charges and discharges the MOSFET capacitance be cancelled by the proximity effect of the opposing currents. This lowers the trace inductance of the Dual Stripline. In addition radiated noise is lowered since the gate traces are enclosed by the ground plane.

Dual Stripline Configuration (Cross Section View)

Figure 1a shows a Dual Stripline transmission line design that has been created to match the drive capability of a 3 ohm drive stage similar to what is in an XRP7714. In the four layers shown in Figure 1a, the top and bottom (cross hatched area) conductors are a power plane or ground, but from an AC perspective both can be considered ground. The two inner conductors on the signal planes are the gate and source leads to the MOSFET. These signals come from the internal driver of the XRP77XX.


Here are some basic guidelines for the design of a Dual Stripline as shown in Figure1a:

  • Close traces, the “D” dimension lowers the intrinsic inductance, L0.
  • Increasing the trace width, W will decrease L0.
  • Increasing copper thickness, T will increase L0.
  • Increasing length will not change Z0 but will increase the amount of parasitic capacitance and inductance that the driver will see. This will add to the losses in the driver.

Designs can accommodate some discontinuities (e.g. vias, unequal traces) to allow for getting a layout routed. These runs are not as critical as many digital signals.

The capacitance is affected by the distance to the ground plane, H and thickness of the trace, T. The thinner the dielectric, the higher is the capacitance. Also the higher the PCB dielectric constant (K) the greater is the capacitance.


Tests were done on a printed circuit board (PCB) using Exar’s XRP7714 digital controller.

The Figure 1b is a block diagram of the XRP7714 and MOSFET connections using the Dual Stripline configuration.

Block diagram of the XRP7714 and MOSFET connections using the Dual Stripline configuration

From a PCB layout viewpoint, each return etch should follow under the gate drive etch on an adjacent signal layer. For the high side MOSFET gate drive (GH1 and LX1) this should be easier to implement. However, for the low side gate drive (GL1 and PGND1) care must be taken to ensure that PGND is not connected in multiple places, which could reduce the benefit of a Dual Stripline configuration.

The two Figures below show the internal Layer 3 layout (Figure 2) and internal Layer 4 layout (Figure 3) of an XRP7714 PCB layout that uses the Dual Stripline configuration as discussed above.

Gate conductors

PGND an LX Return conductors


To verify that the Dual Stripline configuration is performing as intended, three separate tests were conducted. The voltage waveform at the phase node (LX) was measured with a 250 MHz bandwidth oscilloscope and with differential probes directly at the pins of the MOSFETs. In these tests, the input voltage was 12 VDC and the output voltage was 3.3 V with a 12 Amp load.

Test 1 used a DrMOS type power stage so that the gate driver is optimized for the MOSFET while the parasitic inductance and capacitance are minimized since all of the devices are on the same silicon. The DrMOS has an internal driver so that the trace length from the controller to the FETs is not a factor.

Test 2 used discrete MOSFETs being driven by the XRP7714 drivers with a short distance between the XRP7714 pins and the MOSFET gate pins.

Test 3 used the Dual Stripline configuration with the PCB layout shown in Figure 2 and Figure 3 with a distance of 5 inches between the XRP7714 pins and the MOSFET gate pins.

Summary of the Test Results

The reduced ringing in Test 1 with the DrMOS is attributable to the lower parasitics associated with close coupling of the gate drivers and power MOSFETs.

When comparing the results from tests 2 and 3, it can be seen that phase node performance has not been degraded at all by using the longer gate drive traces. Furthermore, it is evident that this technique even compares reasonably well to the optimal integrated drivers on the DrMOS set up.

Lastly, measurements were also made of the gate drive signals for the Dual Stripline configuration to verify that the distance hasn’t prevented the gate driver from exerting proper control over the gate at the point of phase node current commutation. Measurements also showed that the low side gate remains considerably lower than 1.8V when both the high to low and low to high transitions of the phase node occur, ensuring cross conduction cannot occur.


Correct layout is always a vital part of any good switch mode converter design. Experience dictates that adding additional distance between the gate drivers and power MOSFETs in such a design would be a violation of typical design principles. However, this article has shown that when attention is paid to the traces between gate drivers and the FETs, and a few simple Dual Stripline guidelines adhered to, a distance of up to 5” is achievable with virtually no impact on the overall performance of the converter. This in turn allows designers to take full advantage of the higher level of integration offered by the XRP77xx series of programmable multi-channel controllers without having to sacrifice the geographic flexibility afforded by individual POL solutions.

Board side trace configuration

Design example

A brief discussion on impedance, capacitance and inductive calculations

An industry accepted formula for the characteristic impedance (Z0) and capacitance (C0) of a Broad Side Trace configuration is shown below.

C = 0.0882\cdot K\cdot \frac{W}{d}\bigg(1+\frac{d}{\pi \cdot W}\bigg(1+2.3\cdot log\bigg( \frac{2\cdot \pi \cdot W}{d}\bigg) \bigg) \bigg) in \frac{pF}{cm}

Z_0 = \sqrt{L_0 \cdot C_0}

The formulas don’t take into account the affect of the outside ground planes. Their affect will further decrease the inductance so they will be beneficial, and the calculated inductance could be thought of as the worst case. This formula is an approximation based on simplifying assumptions as shown and should be used with the understanding that this is only valid over a range of values, and should be used as guidelines as none will give exact results. There are textbook and Web-based impedance calculators available online that do not consider the valid range of parameters, so user beware!

It is interesting to note that almost all multilayer PCB with ground planes and power planes will introduce a stripline configuration since the signal trace is usually between two ground planes. The unique attribute of the Broad Side Trace and Dual Stripline is that the signal trace and its associated current return trace should be above and below each other as the trace makes its way across the PCB.


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