Posted on 01 March 2019

Extending the reach of JTAG/Boundary Scan

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PXI based Boundary Scan systems featuring advanced test resources

In the recent years, PXI has established its position in the test and measurement industry, especially due to features such as high data transfer rates and small footprint of open, flexible PXI systems.

By Mario Berger, GOEPEL electronic GmbH


Still, there are many areas in which the utilization of PXI is only partially explored. This article illustrates some new ways to utilize PXI for test systems incorporating JTAG/Boundary Scan.

What is PXI?

PXI (PCI eXtensions for Instrumentation) is an open industry standard for modular measurement and automation systems ( Based on and compliant to Compact-PCI, PXI combines the PCI-specification with new instrumentation specific features, taking advantage of the high performance of state-of-the-art PC-systems and their low cost. Based on the high-speed PCI bus, data rates up to 132MB/s are possible.

As opposed to a PCI based system, PXI provides up to 21 slots in a 3U PXI rack in addition to the system controller. In addition, the PXI standard includes EMI and cooling specifications as well as other features promoting easy integration of various modules from different vendors in flexible, high-performance systems:

Trigger Bus for synchronization between modules;
Local Bus for data transfer between modules in neighboring slots;
10 MHz system clock available on all module slots;
Star Trigger signals in a star configuration from Slot 2 to all other slots.

PXI specifies Microsoft Windows 9x/2000/NT or XP as the operating system, providing for a wide range of available application software. The definition of VISA (Virtual Instrument Software Architecture) ensures software compatibility for communication and control between PXI systems and interoperability with Compact-PCI, PCI, VXI and GPIB applications.

PXI, initiated by National Instruments as an extension of the PC internal PCI bus, has enjoyed a rapid and wide adoption in the measurement and automation industry. And the number of vendors and their PXI offerings is constantly growing.

The modularity of a PXI system as well as the many proven software solutions available on the market today allow the users to specify and build a customized, open system for their specific applications. Such a system benefits not only from the high performance of the PCI bus, but also from the many special communication, trigger, and synchronization signals defined in the PXI specification. Those valuable features are in particular utilized in modern PXI based Functional Testers. PXI’s compactness as well as the small price in comparison to other industrial bus systems are further benefits.

Widely adopted by the test industry, PXI presents itself as valuable and useful also for manufacturing test applications such as JTAG/Boundary Scan.

What is JTAG/Boundary Scan?

JTAG/Boundary Scan has been developed in the late 1980s by the “Joint Test Action Group (JTAG)” and was approved as IEEEStandard 1149.1 in 1990. IEEE-Std. 1149.1 defines test resources to be implemented in digital ICs to support a structural interconnect test. Related standards are IEEE-Std. 1149.4 for analog and mixed-signal test, and IEEE-Std. 1149.6 for the test of advanced digital networks.

How does Boundary Scan / IEEE 1149.1 work?

Figure 1 provides an overview of the test resources built into an IEEE-1149.1 compliant device.

Typical Boundary Scan JTAG device

The so-called Boundary Scan Register is made up by the Boundary Scan Cells. Each digital I/O pin of the IC is typically connected to up to three Boundary Scan (BScan) Cells: an input cell to measure the pin’s logic value, an output cell to drive the pin, and a control cell to activate and deactivate the pin driver. In normal mode the BScan Cells do not influence the signals on the pins. In test mode, however, the BScan cells take control over the I/O pins. The internal functional blocks of the device (core logic) are essentially disconnected from the pins at that point. Therefore, by loading the BScan cells with the appropriate values, the pins can be stimulated and observed. This way the Boundary Scan Register (serial connection of all BScan cells) is used to apply test pattern to and to measure response pattern on the IC’s I/O pins in order to perform structural interconnection tests at board and system level.

The main advantage this technology provides is the embedded test access to circuit nodes, reducing or eliminating the need for mechanical access through bed-of-nail fixtures or Flying probes (see figure 2).

Comparing In-Circuit Test with  JTAG Boundary Scan

JTAG/Boundary Scan works around the problems current and future device packaging and board density create for mechanical test access methodologies. Since the test access is accomplished through resources built into the devices themselves, no – or fewer – test points are required on the PCB, which simplifies board layout. Furthermore, for JTAG/Boundary Scan the physical layout of the board is not of interest. Tests can be developed concurrently to the board layout design or even before the layout process begins, since for Boundary Scan test development only the information about pin level connections and the available Boundary Scan resources and non-Boundary Scan device functionality is needed, all of which is available with the schematic of the Unit Under Test. This approach enables the test engineers to evaluate the testability via Boundary Scan and to ensure sufficient overall test coverage, often by combining Boundary Scan with other test technologies. Test programs are available for the first prototype boards and can easily be modified for the final version of the Unit Under test for utilization in production test and even field service. The latter requires flexible and compact test equipment, but what amount of hardware is really needed?

Primarily, access to the Boundary Scan Registers as well as control over the mode of the BScan ICs (normal mode or test mode) is required for Boundary Scan test execution, all of which is done through the IEEE 1149.1 Test Access Port (TAP). The TAP consists of 4 signals: TDI (Test Data In), TDO (Test Data Out), TMS (Test Mode Select), and TCK (Test Clock). An optional fifth signal, the Test Reset, may be implemented. So, the required test equipment includes a Boundary Scan controller to access the TAP, respective software to control the Boundary Scan sequences, and a power supply (Boundary Scan requires the Unit Under Test to be powered up).

Teamwork: PXI based JTAG/Boundary Scan test system

How can Boundary Scan take advantage of instrumentation features made available through PXI? Essentially, the benefits can be summarized with two words: flexibility and versatility. In a minimum configuration, simply adding a PXI Boundary Scan Controllers (figure 3) to the PXI system, and implementing respective software control, immediately allows the execution of applications utilizing the IEEE 1149.1 protocol.

Boundary Scan Controller

The modularity of a PXI system promotes such simple integrations. Simply running Boundary Scan test pattern controlled by a PXI system is nothing new, though. A revolutionary approach lays in surpassing the limits of plain Boundary Scan and in performance improvements. The trigger features PXI offers are the key for such integrations.

Until now, the power supply of the Unit Under Test could not be tested while Boundary Scan vectors were applied. This would be of essential value though. If the power supply does not work properly, then such faults often can be diagnosed only after lengthy debug sessions, which may additionally stress the Unit Under Test (UUT). With Boundary Scan controllers based on PXI this gap in testability can easily be closed. Programmable current sources provided on a PXI card can record voltage and current values throughout the Boundary Scan Test execution. By correlating these recorded values to specific Boundary Scan vectors, events such as Ground-Bounce or shorts to power supply rails on the Unit Under Test can be diagnosed automatically. Also part of the PXI system could be modules providing tools for the measurement and/or stimulation of analog values; all synchronized to Boundary Scan stimulus and response pattern. Such modules support a new quality of extended Boundary Scan applications. Digital I/O modules for the test of the UUT’s peripheral connectors via Boundary Scan are state of the art. However, controlling such modules through the parallel PXI bus synchronized to Boundary Scan pattern applied to the UUT (instead of through a serial IEEE 1149.1 TAP as part of the Boundary Scan chain) allows for a faster test execution and – for a first time – allows the test software to treat UUT and I/O modules as independent units. Thus, typically time intensive Boundary Scan applications, such as In-System Configuration of FLASH devices, can be executed much faster in such an environment.

PXI module family for Boundary Scan applications


These few examples suggest the enormous potential that lays in PXI based JTAG/Boundary Scan solutions. The open, modular structure, combined with the trigger and local bus features, provides an ideal high-performance platform for current and upcoming technology trends not only in the world of Boundary Scan. These new PXI based Boundary Scan modules pave the road for new and advanced Boundary Scan applications.

In 1999, GOEPEL electronic decided as the worldwide first vendor of Boundary Scan test systems to develop a Boundary Scan for the PXI platform. Since then, the company has continuously developed new PXI modules for JTAG/Boundary Scan applications and today offers a wide spectrum of Boundary Scan test equipment for PXI solutions, including Boundary Scan Controllers, programmable power supplies with tracing capabilities, various digital I/O modules, and modules for analog and mixed-signal tests.



1) GÖPEL electronic, Boundary Scan Tutorial, AE0007HE.
2) Heiko Ehrenberg, Incorporating Boundary Scan tools in PXI based ATE systems, AutoTestCon 2003 Paper AU-072 PXI System Alliance, PXI specification,
3) GÖPEL electronic, PXI/PCI Guide 2004.



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