Posted on 23 July 2019

Factorized Power Architecture and V•I Chips

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A Holistic Approach

With each generation of processor, memory, DSP and ASIC, the trend to lower voltages at higher currents continues to challenge the infrastructure needed to support contemporary “loads” with the requisite currents.

By Paul Yeaman, Principal PLE Strategic Accounts, Vicor Corporation


Nevertheless, the fundamental functions of any power conversion system remain unchanged: energy storage, isolation, voltage transformation, and regulation. In recent years, R&D in power distribution, topologies, and control architectures integrated with ASICs, have led to Factorized Power Architecture (FPA) that is a holistic – i.e., a unified optimized system – approach vs. the traditional design compromises.

FPA Description

FPA is an architecture for implementing fast, efficient, and dense power systems by use of building blocks called V•I Chips (Figure 1). V•I Chips are highly integrated devices that use a common package for simplified system design. Each performs a specialized function in a power system, eliminating duplicated functions. Separation of power conversion stages reduces distribution losses in a system, reduces duplicated functions in the DC-DC conversion path, and reduces power dissipation at the point of load while increasing total system efficiency.

The V•I Chips of Factorized Power

V•I Chips are DC-DC conversion building blocks that provide key advantages to the power designer, such as: small size, low weight, high power density, high efficiency, design flexibility, and fast response. V•I Chip components include the PRM™ regulator, the VTM™ current multiplier, and the BCM™ converter.

The PRM provides a regulated output voltage — the factorized bus voltage — from an unregulated input source. It can be removed, or “factorized,” away from the point of load.

PRMs are combined with VTMs to create isolated DC-DC converters, and they can also be used standalone as non-isolated voltage regulators. The VTM provides pointof- load (POL) voltage transformation and isolation. VTMs are used in conjunction with PRMs enabling a complete DC-DC converter with higher density, flexibility, and efficiency.

The BCM provides an isolated intermediate bus voltage to power non-isolated POL converters from a narrow-input-range DC source. The BCM offers superior performance and lower cost than conventional quarter- brick bus converters.

Regulation and Voltage Transformation

In FPA systems, the POL voltage is the product of the Factorized Bus voltage delivered by the PRM and the K-factor (the fixed voltage transformation ratio) of a downstream VTM. The PRM controls the Factorized Bus voltage to provide regulation at the POL. Because VTMs perform true voltage division and current multiplication, the Factorized Bus voltage may be set to a value that is substantially higher than the bus voltages typically found in intermediate bus systems, reducing distribution losses and enabling use of narrower distribution bus traces.

The PRM control system and supporting ASICs enable regulation of the output voltage under control of a choice of control protocols. Under Local-Loop control, the PRM senses its output voltage, regulating the voltage at the load, subject to a “droop” proportional to the VTM output resistance. This “local-loop” protocol provides load regulation within ± 4%. Under Adaptive-Loop control, the PRM compensates for the VTM output resistance; load regulation is typically 1% at the VTM output.

Adaptive Loop compensation feedback is a unique single-wire alternative to traditional remote sensing and feedback loops. It enables precise control of an isolated POL voltage without the need for either a direct connection to the load or for noise sensitive, bandwidth limiting, isolation devices in the feedback path.

Adaptive Loop compensation, illustrated in Figure 2, contributes to the bandwidth and speed advantages of Factorized Power. The PRM monitors its output current and automatically adjusts its output voltage to compensate for the voltage drop in the output resistance of the VTM. ROS sets the desired value of the VTM output voltage, Vout. RCD is set to a value that compensates for the output resistance of the VTM, which, ideally, is located at the point of load. The values of ROS and RCD may be determined by consulting the appropriate table or by calculation.

With Adaptive Loop control, the output of the VTM is regulated over the load current range

The V•I chip bi-directional VC port

Provides a wake-up signal from the PRM to the VTM that synchronizes the rise of the VTM output voltage to that of the PRM. Provides feedback from the VTM to the PRM to enable the PRM to compensate for the voltage drop in VTM output resistance, RO.

The Bus Conversion Function

The BCM may be used as an independent source or as an intermediate bus converter to power non-isolated POL converters. In the latter role, the BCM not only expands the range of IBA (Intermediate Bus Architecture) design tradeoffs in current and power density, it employs a unique capability that can be useful for IBA design architects. The BCM power train offers a unique capacitance multiplication feature. With a BCM, the multiple bulk caps can be removed from the input of the niPOLs to be replaced by a single capacitor at the input of the BCM. Since energy stored in a capacitor is 0.5CV2, a small amount of capacitance at the input to the BCM has the same effect as the bulky capacitance typically added to the input of the downstream niPOLs. When a BCM with a K of ¼ is used, for example, the effective output capacitance is 16x the input capacitance.

Impedance reduction is an additional feature. The characteristic impedance of the capacitor is actually transformed by the K factor squared, so it looks K squared times smaller. The BCM looks like a very low impedance out to about a megahertz, and niPOLS typically switch at about 250 kilohertz. So at 250 kilohertz, the energy drawn from the input comes from the BCM. The BCM looks like a 12-15 milliohm impedance at that frequency, which is less impedance than would be seen from a typical capacitor. The volume of a capacitor increases linearly with the resistance. So a capacitor that is rated for the appropriate amount of voltage here would be four times larger (at K=¼), reducing the overall size of the capacitor.

Paralleling with V•I Chips

In applications requiring higher current or redundancy, VTMs and BCMs can be operated in parallel without adding control circuitry or signal lines. They will inherently current share when operated in an array.

Current sharing accuracy is maximized when the source and load impedance presented to each VTM or BCM within an array are equal. The recommended method to achieve matched impedances is to dedicate common copper planes within the PCB to deliver and return the current to the array, rather than rely upon traces of varying lengths. In typical applications, the current being delivered to the load is larger than that sourced from the input, allowing traces to be utilized on the input side if necessary. The use of dedicated power planes is, however, preferable.

The VTM and BCM power trains and control architectures allow bi-directional power transfer, including reverse power processing from the output to the input. Reverse power transfer is enabled if the input is within its operating range and the module is otherwise enabled. The ability of a VTM or BCM to process power in reverse improves VTM/BCM transient response to an output load dump.

Parallel arrays of BCMs operate much like MOSFETs in parallel. To the extent that the RDS(ONs) are matched, the MOSFETs will share current. To the extent that the output impedances of the BCMs are matched, they will share current. A number of BCMs with parametrically different output resistances in parallel will have sharing imbalances based on those output impedances. However, because they have a positive temperature coefficient, to a certain extent they will equalize their output impedances by the temperature variations that arise from the current imbalances. Essentially, a natural feedback mechanism forces sharing by the temperature differences between the VTMs equalizing out any parametric changes in output impedance.

PRM and VTM Parallel Operation Example

Creating increased power capability by placing V•I Chips in parallel using the PR interface is a simple, straightforward task, especially for most applications where high bandwidth / high slew rates are not required. The paralleling example shown in Figure 3 is a current-sharing higher-power array using two PRM-AL and VTM pairs in a parallel configuration.

PRM-VTM interconnect schematic

Traditional DC-DC converters regulate the output voltage to a set point by comparing a sample of the output voltage to an internal reference voltage, and adjusting either the switching frequency or pulse width to maintain regulation. These converters can operate as constant-current devices, or constantpower devices such that they will maintain voltage regulation up until either the current limit or power limit is reached. In the case of some constant-current devices, the voltage falls and current remains fixed when the limit has been exceeded.

When two voltage-regulated DC-DC converters are placed in a parallel configuration to increase power delivered, simply connecting the inputs together and the outputs together will not result in equal current share. Each converter samples its output and compares it to its reference to maintain the set-point voltage. One device will always have its voltage set point higher than another due to manufacturing variability and circuit impedance imbalance. With two devices operating in parallel as described, one will sense it has more voltage on its output and will sit "idle" because its regulation loop is satisfied.

V•I Chip topologies are unique and behave differently than the prior art. When configured in parallel, the possibility exists for one pair to come up, enter current limit, and shut down while the other pair is doing the same due to the inherent turn-on delays and asynchronous nature of the devices. This prevents them from being configured as traditional converters using the droop-share method. Simply connecting the PR pins and PC pins of the PRM, however, overcomes this scenario and assures accurate current division between the pairs.

Finally, the FPA power distribution architecture is inherently more granular and leverages DC-DC converter functions consistent with efficient power distribution principles and a holistic system. Interestingly, it can also provide all of the benefits of Centralized Power Architectures without the limitation in busing large currents. In fact, with FPA front ends and VTMs at the point of load, a new class of high performance, low-cost centralized power systems becomes possible and attractive.



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