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Posted on 10 January 2019

Failure Mechanisms During Power Cycling

 

The thermo-mechanical stress between materials with different thermal expansion coefficients (CTE) leads to aging of connections when they are exposed to temperature changes. Which of the mechanisms will eventually cause component failure depends on the load and cooling conditions. The further the connection is away from the chip, the longer it takes to heat it up completely. The worse the power semiconductor is cooled, the more all layers are raised to the temperature level of the chip. It is therefore useful for an increase of the power cycling capability to make improvements to the most exterior source of failure (closest to the heat sink). Damage here will increase the ΔT of all connections located above and cause them to fail as well. The development of modules without base plate eliminated "base plate solder" as the source of failure in the Nineties. The introduction of sinter technology to replace chip solder pushes the failure limit for this type of connection further up and makes the bonded connections the weakest link in the chain. The improvements of bonded connections introduced in recent years now result in significantly higher power cycling figures than technically feasible 10 to 15 years ago.

Figure 1 explains the structural details relevant to the life of an IGBT.

Structural details of an IGBT module

Figure 1. Structural details of an IGBT module (connections that are relevant to module lifetime are marked red)

Figure 1 and Figure 2 show that the solder connection of the substrate to the copper base plate is the most critical connection, since it covers by far the biggest area (given average differences in the thermal expansion coefficients of the adjacent materials). For this reason, high quality solders and sophisticated soldering procedures have to be applied in order to avoid deformation and destruction of the module plates also in case of high temperature cycling amplitudes. In addition, DBC substrates are often divided up to keep the absolute difference of the expansion coefficient as small as possible by reducing the solder areas. Other module developments are replacing copper as base plate material by a material with a smaller expansion coefficient (such as AlSiC) or eliminating it completely.

Figure 2 shows the theoretical linear expansion for different layers with an edge length of 1 cm. The bars show the differences true to scale. Huge differences in length are an indication of considerable stress. On the left, the temperature ratios of a typical application condition are assumed with TC =80°C and Tj = 125°C. The temperature gradient in the module has the effect that the copper base plate will only extend to about double the length of the chip despite its 4-fold CTE. Passive heating results in linear expansions that correspond to the CTE ratios, as shown on the right. The table also demonstrates that an AIN ceramic substrate is better adapted to silicon. In turn, the stress between AIN ceramics and copper base plate is increased so that this combination can be used with restrictions only, or not at all. AIN ceramics and AlSiC base plate constitute a better combination in terms of module service life. Al2O3 ceramics are in between the thermal expansion of Si and Cu and therefore make an ideal intermediate layer for modules with a copper base plate. Bond wires are not connected via large area joints. The linear expansion shown here results in wire bending. The comparably small bond foot, however, is subject to particular stress due to the great difference in the CTE of silicon chip and aluminium bond wire.

Linear expansion of different material layers in a power semiconductor module

Figure 2. Linear expansion of different material layers in a power semiconductor module with an assumed edge length of 1 cm. Left: for a temperature gradient in the module as for a typical power cycle; right: for heating up the entire module as for temperature cycling with identical ΔT

Solder fatigue on the base plate

Large area soldering of a module base plate is stressed in particular in slow processes and intense heating. At first, the solder connection will start cracking at the corners. As a result, the thermal resistance of the module will increase. This may cause chip overheating and speed up other failure mechanisms so much that they will then produce a failure. The quality of base plate soldering is safeguarded by temperature cycling tests.

34 mm module with torn off DBC

Figure 3. 34 mm module with torn off DBC (light-coloured areas show solder fatigue)

It has become very obvious that one of the main causes for wear and tear can be eliminated by doing without a base plate and the necessary soldering, as long as the heat transfer from the substrate to the heat sink can be sufficiently ensured by other means and the disadvantages of reduced heat spreading can be compensated.

Solder fatigue in chip soldering

Solder fatigue in chips mostly appears together with damage of the bond wires. The more the whole module heats up, the more the solder connection is strained. Solder fatigue leads to an increase in Rth and the chip temperature, which in turn will cause higher losses and thus a higher temperature difference ΔT in the IGBT. In the end, the aging process is accelerated.

Chip solder fatigue caused by power cycling test

Figure 4. Chip solder fatigue caused by power cycling test, a) Photograph, b) Ultrasound image

The four IGBT chips (Figure 4) on the right of the DBC substrate underwent power cycling, the other IGBT chips and CAL diode chips on the left did not. In the ultrasound image (SAM = Scanning Acoustic Microscope), delamination after power cycling can be seen. The four parallel, jointly current-carrying IGBTs have their hottest spot in the center. It can be clearly seen that delamination starts right there at the inner corners. For larger chips, the temperature gradient over the chip area might result in damage at the center where the temperature ΔT is highest, rather than at the edges, as is usually the case [1]. This effect will become more and more important in the future with an increase of the permissible chip temperature (e.g. to 175°C) and the resulting higher ΔT. The temperature cycling capability of the backside soldering of the chips to the substrate can be improved by

  • using AlN substrates whose thermal expansion coeffi cient differs less from that of Si than is the case with Al2O3
  • substituting the soldering with low temperature joining technique. The connection between chips and substrate is made by sintering silver powder at relatively low temperature and high pressure, which will already minimize thermal stress between the materials during production.

Bond wire lift-off or breakage

In comparison with copper and silicon, aluminium has a relatively high thermal expansion coefficient. This damages the welded connection of the bond feet ("lift-off") and, due to changes in the length of the bond wires, even the kink at the bond foot becomes damaged ("heel crack"). Further movement is caused by temperature related bending of the module base plates and in addition to thermal movement also by mechanical stress (e.g. owing to high current surges). The soft moulding with silicon applied in the power modules will absorb these mechanical vibrations.

Since power modules with rated currents > 10 A per chip have more than one bond wire positioned in parallel, a loss of bond wire contact will not immediately result in component failure. Contact losses will become noticeable by an escalation of the forward voltage in the power cycling test. Those parallel, not yet fully destroyed bond wires must now carry additional current, the bond feet will be heated up even more. Thus their aging process is further accelerated. In the last bond wire left, the current density will then be so high that the metallisation will start melting, an internal arc will occur and eventually the chip will be destroyed. A pure circuit interruption ("open terminals"), however, is very rare in practice.

Bond wire damage

Figure 5. Bond wire damage; a) Breakage and lift-off at the marked area; b) Failure due to bond wire lift-off [2]

The main weak points of bond connections are the aluminium bond wire area right above the ultrasonic bonds, whose crystalline structure is impaired by bonding. Thanks to new wire alloys, improved bonding tools and optimised control of the bonding processes over time, the bond lifetime could be doubled in coming years. Thus, [3] has proven the correlation between the angle of inclination of the bond wire and the maximum number of possible power cycles. The angle of inclination is proportionate to the loop height to width ratio.

Function of bond wire loop height to width ratio in relation to power cycling capability

Figure 6. Function of bond wire loop height to width ratio in relation to power cycling capability [3]

"Bond wire failure" can be eliminated as cause of failure by using double sided pressure contacts, as is found in disk cells, for example. Bond connections in IGBT and diode disc cells have been replaced by pressure contacts with an inherent higher temperature cycling capability [4].

Reconstruction of chip metallisation

This is another aging process that is induced by power cycling. This process is accelerated by high current amplitudes.

Chip metallization before and after power cycling

Figure 7. Reconstruction of chip metallisation, a) before and b) after power cycling [5]

Changes in the chip metallisation gradually increase the chip resistance causing additional losses, higher ΔT and a worse adherence of the bond wires, thus accelerating the failure process. Limiting the repetitive current load (ICRM) is therefore necessary.

References:
[1] Lutz, J. et al.: "Power cycling induced failure mechanisms in the viewpoint of rough temperature environment", CIPS 2008, Conference Proceedings
[2] Amro; Lutz; Lindemann: "Power Cycling with High Temperature Swing of Discrete Components based on Different Technologies", Power Electronics Specialists Conference 2004 (PESC04), Aachen, Conference Proceedings
[3] Ramminger, S.; Seliger, N.; Wachutka, G.: "Reliability Model for Al Wire Bonds Subjected to Heel Crack Failures", Microelectronics Reliability 40 (2000)
[4] Eicher, S.; Rahimo, M.; Tsyplakov, E.; Schneider, D.; Kopta, A.; Schlapbach, U.; Carroll, E.: "4.5 kV Press Pack IGBT Designed for Ruggedness and Reliability", IAS Annual Meeting 2004, Seattle, Conference Proceedings
[5] Hamidi, A.; Kaufmann, S.; Herr, E.: "Increased Lifetime of Wire Bond Connections for IGBT Power Modules", IEEE Applied Power Electronic Conference and Exhibition (APEC), Anaheim, 2001, Conference Proceedings

For more information, please read:

Causes of Failure of Power Semiconductor Devices (PSDs)

Device Failure due to Electrical and Thermal Conditions

Served Out Power Semiconductor Devices

Device Failure due to Incorrect Mounting

 

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2 Responses

  1. avatar Edwin says:

    I think the caption for Figure 7 a and b are flipped. a) is after and b) is before.

     

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    • avatar PowerDahl says:

      Hello Edwin,

      You are correct. Thank you for pointing this out. The image has been updated.

      Regards, PG

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