Posted on 04 August 2019

Feature-Rich Optocoupler Enables IGBT Driving Scalability

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High scalability of an IGBT driving solution and consistent protection measures are essential requirements for a power converter platform design. The ACPL-339J gate drive optocoupler uses dual outputs to drive a current buffer’s upper and lower MOSFETs separately, thus allowing delicate timing control techniques to be integrated in the optocoupler. This design essentially enables current scalability of the buffer stage as the MOSFET pair can be changed to a higher rating one without changing the isolation and driver interface. Therefore, consistency of protection features provided by the optocoupler is maintained.

By Hong Lei Chen, Product Manager, and Ivan Yang, Field Application Engineer, Avago Technologies

One of the requirements in a power converter platform design is the capability of covering a wide range of power ratings. This requires sufficient scalability of the IGBT driving solution to accommodate for different IGBT ratings. For example, in low power (several kW and below) motor drives or inverters, a gate driver circuit with up to 1.5 A output current would be suitable. For a medium power model, such as from several kW to 30 kW system, a 2.5 A output current gate driver shall be used instead. Converters with power rating from tens of kilowatts to hundreds of kilowatts and even megawatts, a current buffer stage consists of BJTs or MOSFETs or both is often needed to boost current driving capability from several amperes to tens of amperes [1, 2]. The current buffer stage can be integrated in a driver module [3], or available as a standalone chip [4, 5]. Figure 1 illustrates the driving current required for different IGBT classes and converter power ratings along with a suitable gate drive part number [1].

Driving current for different IGBT classes

For a platform design, a common gate driver circuit is preferred to cover a diverse power rating with minimum component changes. Therefore choosing a topology with sufficient scalability that’s able to cover very wide current range is the key to achieving this design goal. The ACPL-339J is suitable for such designs. For low power models, the ACPL-339J’s 1 A peak output current is able to directly drive a power switching device with rating up to 1200 V/50 A. For high power models, a buffer stage can be inserted between the ACPL-339J and IGBT. Designers have the flexibility of choosing different current ratings according to given IGBTs without changing the ACPL-339J, as illustrated in Figure 2.

Flexible gate driver design with wide range of current buffer choices

With appropriate design, the buffered gate driver is able to drive IGBT with rating of 1200 V/600 A [8]. Leveraging on MOSFET-based current buffers, the ACPL-339J successfully extends its coverage from low to high power models and provides a highly scalable solution.

Besides driving current scalability, another important consideration is consistent protection measures across different models based on the same platform design. Gate drive optocouplers vary in not only output current, but also in protection features and feedback logics. For instance, the ACPL-330J’s output is normally High without fault; while the ACPL-339J’s FAULT (no overbar) output becomes High when a fault condition occurs. Therefore to maintain consistency across different models, a design shall stick to same gate drive interface once fixed. In this article, using the ACPL-339J with a recommended current buffer and its integrated protection features will be discussed in detail.

Driving current scalability

There are many different kinds of current buffers available. These include the topologies discussed in reference [2] using discrete devices, and integrated buffer chips such as the IXDD630 [4]. The ACPL-339J is optimized to work with a MOSFET-based current buffer given its properties stated below in comparison with a BJT-based counterpart:

  • MOSFET is a voltage-controlled device that requires less current to switch and no DC current to maintain on,
  • MOSFET switches quickly with shorter turn-on time, and
  • Significant lower power loss within the current buffer stage [6, 7].

However, there are mainly two challenges that are needed to be addressed before enjoying the benefits: (1) a simple CMOS buffer structure will suffer large shoot-through current during switching transition period, and (2) input to output logics are inverted when a non-inverting buffer is desired [2]. The ACPL-339J takes care of these challenges using an integrated active timing control technique to prevent cross conduction in the external buffer stage, and factors in the logic inversion in its drive logic block [8].

Connecting the current buffer

Figure 3 shows a simplified inverter application circuit including the block diagram of the ACPL-339J, the current buffer and surrounding components.

A simplified connection circuit including block diagram of the ACPL-339J

Uniquely designed to support MOSFET-based current buffers of flexible current ratings while providing a robust optical isolation barrier, the ACPL-339J has an LED direct input stage (LED1) and dual outputs, VOUTP and VOUTN, to drive P- and N-MOSFET separately. The device includes a Drive Logic & Overlap Protection block to control internal buffers for VOUTP and VOUTN, respectively, and an active timing control technique to provide a “dead time” (both P- and N-MOSFETs of the current buffer are off) between alternate drive pulses. This dead time is usually of sufficient duration to assure that the On states of the MOSFET pair do not overlap under any conditions.

As one can see, connecting in this way allows for the driver circuit design being easily ported over from one inverter model to another. This is done by exchanging the MOSFET pair according to IGBT classes used in different models, without changing the isolation and driver interface. Therefore, this design provides a highly scalable IGBT driving solution.

Selecting MOSFETs

Current driving capability requirement of the MOSFETs, MP1 and MN1 as shown in Figure 3, can be estimated by the IGBT gate charge and desired charge up time. The equation below shows an example:


where Qg is the total gate charge specified in respective IGBT data sheet. For a 1200 V/50 A IGBT, typical Qg is approximately 300 nC.

For charging time of 200 ns, the ICHARGE will be:

ICHARGE = 300 nC / 200 ns = 1.5 A.

The calculated charging current is an average current. Peak current can be estimated by doubling the average current, as a rule of thumb. So for this example, a 3 A peak current MOSFET driver rating will be appropriate. Table 1 lists some recommended MOSFETs with their ratings and part numbers that are suitable for different IGBT classes.

Recommended MOSFETs suitable for different IGBT classes

Note Qg are typical numbers, refer to respective IGBT specifications for actual figures.

Circuit operation

The ACPL-339J consists of 2 LEDs and 2 IC dies, housed in an SO-16 package (Figure 3), providing the input receiving circuitry, the output power stage, and two optical-coupling channels. Along the electrical isolation barrier, it divides into an input side and an output side. The input side includes an LED (LED1) to receive pulse width modulation (PWM) signal, and a Feedback Detector IC to receive fault status feedback signal from LED2, which is located on the output side. Beside LED2, the output side has an IC chip that performs mainly the driving and protection functions. It detects photo signal from LED1 and generates drive logics to separately control VOUTP and VOUTN, which drives the P- and N-MOSFETs of the current buffer, respectively.

The ACPL-339J operates on three supplies: VCC1 of +3.3 V or +5 V (with respect to VGND1), VCC2 of +15 V and VEE of -8 V (both with respect to VE). Under normal operation, PWM signal source directly drives the LED1 of the ACPL-339J, using resistors to limit its current within recommended range of 6 to 10 mA. Choose an MCU with sufficient output current capability as PWM source, or use a buffer stage. Figure 4 shows the ACPL-339J normal operation input-output waveforms.

ACPL-339J normal operation input-output waveforms

Intelligent IGBT protection

Costly IGBTs are the heart of a power converter, and are required to withstand high DC bus voltage. The efficiency and reliability provided by these power devices are of the utmost importance when maximizing a system performance. The ACPL-339J is featured with various IGBT protection functions, including under voltage lockout (UVLO), desaturation detection, “soft” IGBT shutdown, and isolated fault feedback. Appropriate use of these features can provide maximum design robustness and consistent IGBT and power converter protection scheme across different models.

Under voltage lockout

Under certain conditions such as system start up or fault conditions, the supply voltage (equivalent to the fully-charged IGBT gate voltage) can be lower than a desired level. Insufficient IGBT gate voltage can result in high turn on resistance, hence large power loss and even IGBT damage. The ACPL-339J has two UVLO logic blocks, UVLO_P and UVLO_N, to constantly monitor voltage levels of VCC2 and VEE, respectively. When either of these two power supplies is lower than their respective thresholds, the gate driver will block the IGBT from turning on, or shut it down if it’s already turned on.

Desaturation Detection

Besides monitoring supply voltages, the ACPL-339J Output IC also keeps an eye on the DESAT pin voltage, and reports IGBT desaturation fault when this voltage exceeds 8 V. IGBT desaturation can be caused by phase or rail supply short circuits, control signal failures, and overload conditions. Under desaturation condition, the IGBT current and power dissipation increases drastically, possibly leading to catastrophic failures due to overheat. To protect IGBT, the ACPL-339J monitors its collector-emitter voltage, and triggers an IGBT shutdown sequence if the collector-emitter voltage exceeds a certain level. Table 2 shows the ACPL-339J inputs and outputs truth table according to the application circuit shown in Figure 3.

ACPL-339J application circuit operation truth table

Corresponding status of the current buffer MOSFETs and the IGBT are also included in the table to help understand the circuit operation.

From the truth table, it can be observed that the ACPL-339J outputs (VOUTP, VOUTN, VGMOS and FAULT feedback) are controlled by combinations of LED1 input and conditions of UVLO and DESAT. LED1 input and DESAT condition are ignored when UVLO fault is triggered. When UVLO fault is cleared, and LED1 is On, the DESAT condition will determine the outputs. In this way the UVLO and desaturation detection features work together closely to ensure seamless IGBT protection [8].

Soft shutdown

When an IGBT desaturation fault is detected, the ACPL-339J will shut down the IGBT immediately but “softly” by transferring the gate control from MN1 and MP1 to MN2. During soft shutdown process, VOUTP goes High and VOUTN goes Low, VGMOS switches from Low to High to turn on MN2. MN2 and RS slowly discharge the IGBT gate at a decay rate corresponding to the time constant of RS and IGBT gate capacitance (denoted as CIN, not shown in Figure 3). For example, given RS of 330 Ω and CIN of 10 nF, the decay period is 4.8 × 330 Ω × 10 nF = 15.8 μs [8]. This is a much slower, or “softer”, shut down process compared to the normal turn-off timing through MN1 and RG of 5 Ω. Change RS to a larger resistor say 1 kΩ for even longer shutdown time. Figure 5 to Figure 7 show IGBT shut down timing (gauged by gate voltage fall time from 90% to 10%) for normal operation, soft shutdown with 330 Ω resistor, and soft shutdown with 1 kΩ resistor, respectively.

Gate voltage fall time of 260 ns in normal operation shutdown

Gate voltage fall time of 7 μs in soft shutdown with 330 Ω resistor

Gate voltage fall time of 17 μs in soft shutdown with 1 kΩ resistor

Measurements were done based on the ACPL-339J typical application circuit (Figure 3) with an IGBT FF50R12RT4 connected. Soft shutdown protection is a local IGBT protection mechanism; shut down action is immediately triggered when DESAT pin voltage exceeds 8 V to ensure timely reaction to high risk of damage fault conditions such as short circuit. On the other hand, soft shutdown reduces the IGBT current to zero in a controlled manner to avoid potential IGBT damage from over voltages due to inductive load. Along with DESAT trigger, fault status is transmitted back to the microcontroller via LED2 and FAULT pin, as shown in Figure 6.


Uniquely designed to work with MOSFET-based current buffer capable of diverse current ratings to drive IGBTs, the ACPL-339J makes it easier for system engineers to design a hardware platform that can be easily ported over. It provides a cost effective solution to maximize scalability of an IGBT gate drive design for motor control and power conversion applications ranging from low to high power ratings.

[1] “Main Applications and Selection of Gate Driver Optocouplers, Application Note 1335,” Avago Technologies, May 12, 2019.
[2] Yang Xue, Zhiqiang Wang, L.M. Tolbert and B.J. Blalock, “Analysis and optimization of buffer circuits in high current gate drives,” IEEE Transportation Electrification Conference and Expo, 16-19 June 2019.
[3] “2SP0325T Target Description & Application Manual,” CT-Concept Technologie AG, September 3, 2019.
[4] “IXDD630 30-Ampere Low-Side Ultrafast MOSFET Drivers, Data Sheet,” IXYS, October 15, 2019.
[5] “IRF7343 Dual N and P Channel MOSFET, Data Sheet,” International Rectifier, April 11, 2019.
[6] Yong Li, “Why consider a power BJT rather than a MOSFET?” EE Times, October 25, 2019.
[7] Chun Keong Tee, “Driving and Protecting IGBTs in Inverter Applications,” Power Electronics, August 30, 2019.
[8] “ACPL-339J Dual-Output Gate Drive Optocoupler Interface with Integrated DESAT Detection, FAULT and UVLO Status Feedback, Data Sheet,” Avago Technologies, AV02-3784EN, June 10, 2019.


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