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Posted on 03 July 2019

Feedback Loop Op Amp Limitation Considerations

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Limit wherever possible the level of noise coming into the signal chain

Pulse-width-modulated (PWM) converters have many gain elements in the feedback loop. These elements provide the means to regulate the converters output. Examples will be examined and discussed in terms of their impact on the control loop.

By John Bottrill, Senior Applications Engineer, Texas Instruments

 

The operational amplifier (op amp) in the world of PWM converters is the equivalent of the CPU in the computer. The output of an op amp is the signal used by the control IC’s comparator to define the pulse width of the power switch.

Most, but not all, PWM control ICs have internal op amps. In most cases, the data sheet gives a typical gain-bandwidth product as a frequency at zero dB and a typical DC gain. If the designer takes these numbers and assumes a –20dB per decade roll-off from the DC gain level to the zero dB cross over, the typical gain profile of the op amp can be plotted. For this discussion, we will use the UCC2842 as the typical control IC. The UCC2842’s internal op amp and the TL431 used for the adjustable precision shunt regulator have similar gain curves, so we will use one curve for both.

The control IC has a minimum unity gain-bandwidth product at 0 dB of 0.7MHz and a minimum DC gain of 65dB. The designer assumes that the gain and phase are as shown in Figure 1. These numbers are close to the gain curve for a shunt regulator, so we will use them in this discussion.

Typical gain (1a) and phase (1b) of an error amplifier

As long as the control loop gain requires the op amp’s gain to remain below the limits imposed by its gain-bandwidth curve, the converter operates correctly.

Sometimes designers try to ignore these limits, which is problematic (see Figure 2).

Gain (a) and phase (b) requirements identified

If the designer needs the limits defined in Figure 2, he can not achieve his goal. The op amp limitations come into play and he gets a gain and phase that is a combination of the two. The phase and gain are as desired until the op amp limits are encountered. See Figure 3 where all three traces are shown. Not only is the gain less than desired, but the phase-shift has significant differences than those calculated.

Gain (a) and phase (b) of op amp limits required gain and phase; and actual gain and phase differences

In a situation like this the designer must revise the design to be less than the gain of the op amps limitation over the entire loop.

Look at Figure 4 and remember to maximize the gain of each stage within the parameters of the device used starting at the point where the output is sensed. This affords the highest signal-to-noise ratio (SNR) in the feedback loop.

Converter feedback loop

If you have a small gain at the start and a large gain at the final stage, you have a low signal with a lot of noise at the input to the final high-gain stage. In the final gain stage, the noise and signal are amplified.

Conversely, if you maximize the error signal at the first stage before noise gets into the loop, you are transmitting a large signal with a high SNR to the final stage. This amplifies both signal and noise, but the level of amplification needed is significantly lower and the SNR remains high resulting is the cleanest signal possible.

To further clarify, let’s look at a typical converter where the feedback loop is like that in Figure 4.

The designer has control over three main gain blocks.

Stage 1 is the input resistor R1 and the feedback network consisting of resistor R2, and capacitors C1 and C2. The gain is defined as the impedance of the series connection of R2 and C1 in parallel with C2, all divided by R1. In this case, decreasing R1 results in the gain curve retaining the same shape, but is higher.

Stage 2 consists of R3, R4, R5 and the optocoupler. The gain here is the impedance of the parallel combination of R4 and R5 times the CTR of the optocoupler, all divided by R3. Increasing R4 or decreasing R3 increases the gain.

Stage 3 consists of R6 and R5 and is simply R6 divided by R5. Increasing R6 and decreasing R5 increases the gain.

The total gain of this network must be such that at the planned crossover frequency the gain of this network times the gain of the power stage (COMP to OUTPUT gain) is equal to 1 or 0 dB. On paper, it appears there are multiple ways to achieve this. But, as in all things, there are tradeoffs.

If you lower the gain of stage one so that you are well within the op amps limits, A1, you can increase the gain of the control IC’s built-in amplifier (stage 3), and everything should be good.

However, this ignores the noise sources in the converter. These should be identified and evaluated. If they are excessive, they should be filtered.

One of the main noise sources is the secondary bias voltage source that provides current to the optocoupler. Any noise on this point is translated into current through the optocoupler, and is amplified through the remainder of the circuit.

Follow this design strategy for optimal results. First, determine the maximum gain that can be achieved through the A1 amplifier without violating the op amp’s parameters (see Figure 3) over the frequency range of the error amplifier. You need to control the amplifier over the complete frequency range so you do not run into the op amp’s limitations. Next, filter the noise on the secondary bias to eliminate the noise as much as is possible.

Having established the gain of stage one, you have to allocate the gain stages two and three. The same applies to stage two. Achieve the maximum gain that you can through the optocoupler that allows you to have the voltage variations needed on the COMP pin. This allows for the variations in load and input voltage while maintaining regulation. These variations have to take into account the offsets in the COMP voltage needed to cover the full range of duty cycles from zero to maximum duty.

This range is defined in the parts data sheet. In the case of the UC2842 (see Figure 5) there are three things to note. The two diodes between the COMP and the current sense comparator pin (1.2V voltage drop), the two resistors that reduce the signal by a nominal factor of three (2.85 to 3.15) and the maximum input signal to the current sense pin of between 0.9-1.1V.

Control IC block diagram

This means that the maximum signal for the COMP pin should be ((1.1 V x 3.15) + 1.2V), or about 4.7V with a minimum of under 1.2V (say 0.9V).

Once these are known, the design should attribute the maximum achievable gain to the optocoupler circuit as this will give the best SNR of this stage.

Conclusion

It is important to maximize the SNR throughout the signal chain starting at the sense point in the circuit. This is done by keeping the signal and gain at stage one as high as possible. If the signal coming out of stage one has a high level of noise, later amplification will amplify both the signal – and the noise.

Limit wherever possible the level of noise coming into the signal chain, for instance filter the bias voltage for the optocoupler. Remember that layout has noise. Keeping these things in mind will improve the probability of success without having to do another layout.

 

 References:

Download datasheets and other technical documents:
1) www.ti.com/ucc2842-ca
2) www.ti.com/tl431-ca

3) Ask questions, share knowledge, explore ideas and help solve problems with fellow engineers at TI’s E2E™ Community power forum: www.ti.com/powerforum-ca

 

 

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