Elegant active power factor correction circuit achieves up to 99% efficiency
The widespread use of active Power Factor Correction (PFC) circuit is becoming even more popular as government agencies demand more effective use of grid supply capacities. A typical PFC circuit includes a diode bridge for rectifying the ac source and a boost stage to force the input current proportional to the input voltage. The rectifier bridge consumes a significant part of the circuit loss; therefore, many topology innovations for bridge-less PFCs have emerged. But most suffer from either common-mode (CM) electromagnetic interference (EMI) or other issues and, therefore, are not practical.
By YiFeng Wu and Liang Zhou, Transphorm Inc.
One unique topology called the totem pole PFC has both simple power loops and low EMI . However, this topology demands very-low reverse recovery charges (Qrr) for the MOSFET body diodes – not possible with high-voltage silicon (Si) MOSFETs. With the advent of Gallium Nitride (GaN) power devices  , new 600V-class low Qrr transistors make this highly promising circuit a practical reality.
The evolution of representative PFC topologies is shown in Figure1. A traditional PFC circuit (Figure 1a) consists of a slow-recovery full-bridge line rectifier (D1-D4), a fast boost diode (DB) and a fast transistor switch (SB). In addition to DB or SB, the main current passes through two of the four slow diodes at a given time, which can account for an efficiency loss by 0.6% to 1.2% (at high line and low line, respectively) due to the forward diode drop.
The basic bridge-less PFC (Figure 1b) eliminates all slow diodes, but requires two fast diodes (DB1 and DB2) and two fast switches (SB1 and SB2) . The main current path includes only one switch, plus either one diode or another switch, capable of a significantly higher efficiency. However, both ac input nodes during the negative ac cycle are floating with respect to the two dc output terminals, leading to a high CM EMI . For this reason this topology has limited practical use.
Attempts have been made to modify the basic bridge-less PFC for lower EMI. A successful example is the dual-separate-boost bridge-less PFC, shown in Figure 1c . Employing two boost inductors (LB1 and LB2), two fast diodes (DB1 and DB2) and two fast transistors (SB1 and SB2), in addition to two slow-recovery rectifying diodes (D1 & D2), this PFC ensures the potential of one ac input node to be effectively tied to an dc output terminal at any given time. Consequently, this approach significantly reduces CM noises and has earned popularity among power circuit designers . However, this circuit requires the largest number of fast devices (DB1, DB2, SB1 and SB2) and inductors (LB1 and LB2), yet eliminates only one diode drop compared to the traditional PFC shown in Figure 1a.
Figure 1d shows the totem pole bridgeless PFC with two fast devices (SB1 and SB2), one inductor (LB) and two low-cost, slow diodes (D1, D2). The ability to ensure low EMI is realized by the fact that one ac node is always clamped by a slow diode to either the top or bottom of the two dc output terminals. Additionally, no voltage drop of a fast diode is involved, offering potential for further efficiency enhancement.
The difficulty of implementing this circuit lies in the fact that during dead-time, when both transistor switches are off, one of the body diodes is turned on to allow free-wheeling current in continuous current mode (CCM) operation. In the subsequent hard-switching event, the Qrr of the body diode in a highvoltage Si MOSFETs could cause significant current-voltage spikes, making the circuit unstable in addition to causing high switching losses. The key to implementing a successful totem pole PFC relies on new generation semiconductors with simultaneously low on-resistance and low recovery charge.
GaN TOTEM POLE PFC
The industry’s first qualified 600-V GaN HEMTs (high electron mobility transistors) made on a low-cost Si substrate have been introduced by Transphorm Inc. These firstgeneration GaN power devices show a low on-resistance of 0.15 ohm typical and are capable of reverse conduction during dead time with a low Qrr of 54 nC, which is 20 times lower than state-of-the-art Si counterpart (Figure 2). These features can remarkably expand operation space of a hardswitched bridge. Moreover, these devices are offered in Quiet-tabTM configurations with choices of the metal tab connected to the drain or source terminals. When a drain tab package is used for the high-side device (e.g., SB2 in Figure 1) and a source tab as low-side device (e.g., SB1 in Figure 1), the capacitive coupling between device and heat sink is minimized, further reducing EMI.
A GaN HEMT totem pole PFC in CCM mode focusing on minimizing conduction losses was designed with a simplified schematic (Figure 3a). It consists of a pair of fast GaN HEMT switches (Q1 and Q2) operating at a high pulse-width-modulation (PWM) frequency, as well as a pair of slow but very-low resistance MOSFETs (S1 and S2) operating at a much slower frequency (60Hz). The primary current path includes one fast switch and one slow switch only, with no diode drop. The function of S1 and S2 is that of a synchronized rectifier, as illustrated in Figures 3a and 3b. During positive ac cycle, S1 is on and S1 off, forcing the ac neutral line tied to the negative terminal of the dc output. The opposite applies for the negative cycle.
In either ac polarity, the two GaN HEMTs form a synchronized boost converter with one transistor acting as a master switch to allow energy intake by the boost inductor (LB) and another transistor as a slave switch to release energy to the dc output. The roles of the two GaN devices interchange when the polarity of the ac input changes, therefore each transistor must be able to perform both master and slave functions. To avoid shoot through, a dead time is built in between two switching events during which both transistors are momentarily off. To allow CCM operation, the body diode of the slave transistor has to function as a free-wheeling diode for the inductor current to flow during dead time. The diode current however, has to quickly reduce to zero and transition to the reverse blocking state once the master switch turns on.
This is the critical process for a totem pole PFC, which previously led to abnormal spikes, instability and associated high switching losses due to the high Qrr of the body diode in modern high-voltage Si MOSFETs. The low Qrr of the GaN switches allow designers to overcome this barrier. As seen in Figure 4, inductive tests at 400-V bus using either low-side or high-side GaN transistor as a master switch show healthy voltage waveforms up to inductor current exceeding 12 A. With a design goal of 1 kW output power in CCM mode at 230V ac input the required inductor current is 6 A. This test conforms a successful totem-pole power block with two times the current overhead.
A PFC has been implemented on a fourlayer PCB, as shown in Figure 5. The slow switches (S1 and S2) are 600V super junction MOSFETs with 0.1 ohm on resistance. The inductor is made of a MPP core with inductance of 1.3 mH and a dc resistance 88 mohm and is designed to operate at 50 kHz. Drain-tab and source-tab surface-mount GaN HEMT packages are used with one mounted on the top and another on the bottom side for the shortest electrical lengths between these fast switches, which minimizes power loop inductances.
A simple 0.5-A rated high/low side driver IC with 0/10 V as on/off states directly drives each GaN HEMT. A low-cost fixed-point 60 MHz DSP controller (TMS320F28027DSP) handles the control algorithm in this first version of prototype. The voltage and current loop control is similar to conventional boost PFC converter. The feedback signals are dc output voltage (VO), ac input potentials (VACP and VACN) and inductor current (IL). The input voltage polarity and RMS value are determined from VACP and VACN. The outer voltage loop output multiplied by |VAC| gives sinusoidal current reference. The current loop gives the proper duty-ratio for the boost circuit. The polarity determines how PWM signal is distributed to drive Q1 & Q2. A softstart sequence with a duty ratio ramps is employed for a short-period at each ac zero-crossing for better stability.
Performance as a function of output power measured with a Yokogawa WT1800 power analyzer at 230 Vac input and 400 Vdc output is shown in Figure 6. A peak efficiency of 99.0% is achieved at 400 W while the overall efficiency is >98.6% from 180W to 1kW. This outstanding performance from a simple topology is attributed to higher performance features of the new wide band-gap GaN power devices.
Although new device technologies that continuously improve performance of popular circuits is desirable, a higher impact can be achieved if a development enables new functions and revives a dormant topology to outperform its existing counterparts. The advent of high-voltage GaN power transistors makes this advancement by enabling PFC circuits that were previously impractical to implement. The simultaneous benefits of low on-resistance and low reverse recovery charge from the first-generation GaN-on-Si HEMT are key to building a long-awaited totem pole PFC.
Compared to traditional topologies, the GaNon- Si PFC circuit consists of the fewest number of fast power devices and features the least resistance current paths without a diode drop, thereby achieving state-of-the-art conversion efficiency. As further circuit discoveries and innovations are implemented, the power electronics industry can benefit tremendously from the introduction of GaN power devices.
 J. C. Salmon, “Circuit topologies for PWM boost rectifiers operated from 1- phase and 3-phase ac supplies and using either single or split dc rail voltage outputs,” in Proc. IEEE Applied Power Electronics Conf., Mar. 1995, pp. 473–479.
 Y.-F. Wu, R. Coffie, N. Fichtenbaum, Y. Dora, C.S. Suh, L. Shen, P. Parikh and U.K. Mishra, "Total GaN Solution to Electricity Power Conversion", the 69th IEEE Device Research Conference, Conference Digest, p217-218, June 20-22, 2011.
 Y.-F. Wu, D. Kebort, J. Guerrero, S. Yea, J. Honea, K. Shirabe and J. Kang, “High-frequency GaN Diode-Free Motor Drive Inverter with Pure Sine-wave Output”, PCIM Europe 2012, Conference Digest, p76-83, Nuremberg, May 8-10, 2012.
 D. M. Mitchell, “AC-DC converter having an improved power factor,” U.S. Patent 4 412 277, Oct. 25, 1983.
 H. Ye, Z. Yang, J. Dai, C. Yan, X. Xin, and J. Ying, “Common mode noise modeling and analysis of dual boost PFC circuit,” in Proc. Int. Telecommunication Energy Conf., Sep. 2004, pp. 575–582.
 A. F. Souza and I. Barbi, “High power factor rectifier with reduced conduction and commutation losses,” in Proc. Int. Telecommunication Energy Conf., Jun. 1999, pp. 8.1.1–8.1.5.
 L. Huber, Y. Jang, and M. M. Jovanovic, “Performance evaluation of bridgeless PFC boost rectifiers,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1381–1390, May 2008.