Posted on 02 July 2019

GaN Transistors - Grrr or Great?

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Great, but be careful of what you wished for...

The data sheet specifications of the new GaN transistors cannot tell you all you need to know about these exceptional devices. This note will not enable you to walk on water – but you will know where a few of the stepping stones are. The note will also cause some good-natured angst - because it is also an open letter to GaN suppliers.

By John Roberts – CTO, GaN Systems Inc. Ottawa, Ontario Canada

This year we will see numerous companies introducing real, but not ideal, high voltage GaN transistors. Several of these new devices will be rushed-to-market cascode structures. They will be delivered only to select customers who will be required to sign a non-disclosure agreement. This will include additional clauses restricting any reverse engineering activity and it could even include a return-of-sample policy; this note will explain why.

GaN transistors clearly pose a very serious threat to the purveyors of high speed, high performance MOSFET devices. The projected low cost of GaN on Si transistors even allows for the possibility that IGBT devices could be displaced from their dominance of the lower speed, 650V, very high current power applications. The market opportunity is shown in Figure 1.

Silicon power switching device market

Competitive commercial imperatives, perceived and real, are driving venture capital interest, visits from M&A mavens, strategic investor activity, alliance arrangements and an overwhelming, even oppressive, interest at the trade shows we attend. This explains the extra ‘legal-eagle’ work you will see inserted in your usual benign non-disclosure agreement. The other issue is of course the immaturity of the devices. There is also no certainty that in your application combined with your unfamiliarity with the extraordinary speed of these transistors, that you will not over-stress the GaN transistor. None of the GaN protagonists will want you to propagate your dramatic failure stories.

The issue of voltage overshoot and overstress is of major concern and it needs to be addressed by the GaN suppliers. What follows is a tentative approach towards the creation of suitable standards for GaN transistors and diodes.

The voltage rating?

A series of de-facto operating voltage 'standards' have emerged as shown in Table 1. However because GaN devices have no avalanche specification you would expect they would have to be at least capable of withstanding stress voltages ranging to perhaps 20-25% higher than the rated operating voltage. Your surmised safety factor means that a 650V rated device would be expected to survive repeated voltage excursions that may reach 800V.

Unfortunately, the simplistic safety margin concept, tabulated in Table 1, is flawed. It is necessary for you to recognize that our GaN transistors are similar to 'ceramic capacitors'. That means, at breakdown, they are destroyed. Michael Briere, answering a question at the 2012 APEC, stated this with disarming explicitness. He did not mention the excitement of the event!

Mrinal Das of Cree [1] has described the derating evolution of high voltage SiC devices. The amount of the derating needed naturally reduces as the device technology matures. Writing in 2011, Das described the rating of the Cree 1200V SiC MOSFET. At that time the device had a 1700V median avalanche breakdown. An accumulation of manufacturing and field data would typically allow a smaller safety margin to be chosen. Perhaps at this time, 2013, the SiC device rated at 1200V would have a 1500V median avalanche breakdown. The Table 1 shown above for GaN devices therefore implies perhaps a certain improper arrogance - we have an immature and very different technology - we cannot rate our 1200V devices as shown. We cannot for example establish that we have the 300V margin at 1200V that is shown.

The operating voltage rating and the 'breakdown' voltage rating

The rational looking chart shown in Figure 1 has the wrong premise because of course GaN devices have no repeatable exercisable breakdown voltage capability.

The real voltage rating - blocking voltage Think blocking voltage. The answer for GaN is to develop leakage current limits for each device size. International Rectifier [2] has shown typical leakage current results for its 600V cascode. This achieves a leakage current which is less than 50nA per mm of gate width. The device was required to block, at and above, the rated voltage. The leakage current at 150oC was considered acceptable up to 400nA per mm. These low leakage numbers suggest that the normally- on GaN device used in the IR cascode uses a MIS gate structure. A conventional Schottky gated device would show higher leakage. The same principle applies however - think blocking voltage and use the repeatable, measurable leakage current criteria suggested by IR. In place of 'Minimum breakdown Voltage' shown in Table 1 use the phrase "Transient Drain to Source Voltage" used by Transphorm and further also define the transient time of the voltage excursion plus the voltage excursion.

Packaging and performance

The simple cascode circuit does not provide for slew rate control so that the PC board layout is critical. In addition, gate drive characteristics are in part controlled by the internal series source inductance of the package. This can be as high as 4-6nH for a leaded package. Despite the apparent success of Transphorm in adapting the TO-220 package to make it usable for GaN applications all the GaN suppliers (including Transphorm) intend to move towards using the 5x6mm or 8x8mm PQFN packages. The large land area of the 8x8 PQFN allows for the inclusion of custom IC drivers which provide the possibility of adding features such as slew rate control. PQFN packages as large as 12x12mm allow complete half bridges and drive circuitry to be included. The level of hybrid integration can be taken further and it is possible to envisage that a complete totem pole PFC can be integrated. This circuitry is only made feasible by using GaN devices because they have very low Qrr [3]. The Qrr of the SJ MOSFETIPL60R199CP, for example, is 5500nC while the Qrr of the Transphorm and GaN Systems GaN cascodes is ten to twenty times lower - 16.2 to 54nC for devices with lower on-resistance. The GaN suppliers need to identify and demonstrate the overwhelming advantage of the GaN cascode in selected applications. The Transphorm 'PFCT' initiative [3] is a notable first step in this direction.

During the development phase of GaN it has been satisfying to note the advantages of GaN in terms of specific on-resistance and figure of merit. Contrary to our propaganda however there is new life in the SJ MOSFET concept. As shown in Figure 2 Infineon expects to introduce in 2013/2014 600V SJ MOSFETs with a figure of merit of 3.4. Our expected ten to one advantage needs to be re-established by improvements to the cascode. These may be derived from the advent of robust, low voltage normally-off GaN transistors to replace the discrete MOSFET we now use.

The 600/650 V figure of merit contest, SJ vs. GaN


GaN devices will re-educate engineers in many disparate ways. The spectacular uncontrolled switching speed of the simple cascode structures will produce EMI and voltage overshoot issues not previously experienced. Essentially the GaN cascode structure is a power microwave integrated circuit. When the low voltage MOSFET is driven with a conventional MOSFET driver, the cascode will provide switching speeds of between 50 and 100V / nS while switching 20 to 50A. The packaging issues therefore need to be addressed. A standardized package should be developed that allows for a source sense connection and which further allows for minimum loop inductances to be achieved. Michael Briere has called for the GaN suppliers to develop standards for the qualification of GaN devices. This idea needs to be expanded to include second source arrangements, common test methods, and also to enable packaging standards to be produced.

[1] Mrinal K. Das, "Commercially Available CREE Silicon Carbide Power Devices: Historical Success of JBS Diodes and Future Power Switch Prospects", Proceeding of the 2011 CS MANTECH, Palm Springs, California, USA, May 16-19, 2011, pp. 315-317.
[2] Michael A. Briere, "So What's All This GaN Stuff Anyways?", PSMA Power Technology Roadmap, 2013, pp. 363.
[3] YiFeng Wu and Liang Zhou, "GaN Power Devices Enable High Efficiency Totem Pole PFCT", Bodo's Power Systems, pp. 40-42, May, 2013.


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