### Categorized |Power Design, Power Devices, Power Modules, Thermal Management

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Posted on 26 December 2019

# Heat Dissipation and Thermal Resistance in Power Modules

In order to utilize the theoretical current capability as much as possible, power losses have to be optimally conducted through the connection layers - and for modules also through the insulation layers - to the heat sink. The quality of dissipation for the heat losses Ptot generated during forward on-state and blocking state and during switching is expressed by the temperature difference

$\Delta T_{j-s} = T_j - T_s$

between chip (chip temperature Tj ) and heat sink (heat sink temperature Ts ) which is as low as possible. It is quantified as the (stationary) thermal resistance R th(j-s) or (transient) thermal impedance Z th(j-s) .

$R_{th(j-s)} = \frac {T_j - T_s}{P_v}$

In the past, a "v" for "virtual" preceded the index of the junction temperature (Tvj), since "the" junction temperature does not exist, but merely an equivalent measurement or computed value is used.

For modules with base plate, the value for the outer thermal resistance or impedance is specified as Rth(c-s) or Zth(c-s) (base plate to heat sink) and is distinguished from the inner value Rth(j-c) or Zth(j-c) (chip to base plate):

$R_{th(j-s)} = R_{th(j-c)} + R_{th(c-s)}$

$Z_{th(j-s)} = Z_{th(j-c)} + Z_{th(c-s)}$

For modules without base plate, it is not possible to measure these values separately without seriously interfering with the thermal system. For this reason, only the total resistance between chip and heat sink is specified for these components. Low power components are also specified with reference to the ambient temperature. The rating equation for thermal resistance

$R_{th} = \frac{d}{\lambda \cdot A}$

(d = material thickness, λ = heat conductivity, A = heat flow area)

can be used to deduce which inherent module quantities influence the heat dissipation capability or Rth(j-s) and Zth(j-s):

• Chip (area, thickness, geometry and layout)
• DBC substrate design (material, thickness, structure on the substrate upper)
• Material and quality of the chip/substrate connection (solder, adhesive, ...)
• Presence of a base plate (material, geometry) - Rear soldering of the substrate to the base plate (material, quality)
• Module assembly (surface qualities / thermal contact to heat sink, thickness and quality of thermal paste or thermal foil)

In conjunction with the equation for thermal capacitance

$C_{th} = s \cdot V,$

the elements of the thermal equivalent circuit can be calculated from the geometry layer by layer (s = heat storage characteristic, V = volume). Heat spreading must be factored in to area and volume calculations. A conflicting effect that has to be considered is mutual chip heating in complex power modules (thermal coupling). The calculated theoretical thermal resistance value will often be lower than the actual measured value. The reason for this often lies in the uncertainties observed in heat spreading and thermal coupling, as well as impurities in the border layers which have not been considered in the modelling. For this reason, this type of modelling is not particularly well suited to complex power electronic systems. Normally, the computed Rth values are adjusted to the measured total of Rth with the aid of a weighting factor.

 Material Heat conductivity λ [W/(m*K)] Heat storage charac- teristics [kW/(m³*K)] Thermal expansion coeffi cient α [10 -6 /K] Silicon 148 1650 4.1 Copper 394 3400 17.5 Aluminium 230 2480 22.5 Silver 407 2450 19 Molybdenum 145 2575 5 Solders ~70 1670 15 – 30 Al2 O3 -DBC 24 3025 8.3 AlN DBC, AlN-AMB 180 2435 5.7 AlSiC (75% SiC) 180 2223 7

Table 1. Heat conductivity, heat storage characteristic and thermal expansion coefficient for materials that are frequently used for packaging

In combination with the cooling and ambient conditions, Rth(j-s) determines the maximum module ratings for thermal losses. The development of power semiconductor modules is therefore always associated with the reduction of the number of layers, the reduction of layer thickness (0.63 mm → 0.38 mm for ceramics), and the use of materials with improved thermal conductivity (AlN, graphite). This development, however, is limited by insulation voltage and mechanical strength requirements.

The thermal conductivity of the individual layers and the heat flow area is taken into account. Consequently, enlarging this area by improving heat spread would reduce the thermal resistance of the subsequent layer. Although a thinner copper layer would lead to a lower thermal resistance in a one-dimensional model, in the real three-dimensional space, Rth would in fact increase as a result of reduced heat spreading. Thicker metal layers in the DBC substrate provide thermal advantages; however, they also increase thermal stress within the substrates.

Heat spreading depends not only on the material properties of the given layer, but also on those of the subsequent layer. A sufficiently high potential (temperature difference) must build up so that the heat flow can overcome a poorly conducting layer. This will then result in increased transverse heat conduction (heat spreading) in a layer with good thermal conductivity located above.

A reduction in thermal resistance could be obtained using materials with particularly good transverse thermal conductivity, whereas solutions such as "Silicon on Diamond" (SOD) will probably continue to be reserved for niche markets.

### Proportion of thermal resistance caused by the layers

Figure 1. Influences on the internal thermal resistance of a 1200 V power module, chip surface 9 mm * 9 mm: a) for DBC substrates (Al 2 O 3 ) on Cu base plate, 100 μm TIM; b) for DCB substrates (Al 2 O 3 ) without Cu base plate, 25 μm TIM

Figure 1 illustrates the shares for the aforementioned variables affecting Rth(j-s) for the most common module layouts using Al2 O3 Direct Bonded Copper (DBC) substrates with or without copper base plate.

In both cases, the biggest share of the thermal resistance (approx. 50%) from chip to heat sink is caused by the thermal paste (TIM – thermal interface material). This seems strange at first, since the base plate promises better heat spreading and thus a lower influence from the thermal paste layer. However, base plates never come into full contact with the heat sink across the entire surface owing to inevitable bending due to the ceramic soldering. This effect is known as the bimetal effect and occurs when two materials with different coefficients of thermal expansion are joined by soldering. It cannot be compensated for even with prebent base plates. Bending is not constant but varies over time, since the solder flows, thus relieving some of the stress. Bending also changes as a function of the application temperature. Even an ideally shaped base plate would only rest on the heat sink at one temperature point.

Base plates that are bent in this way are only pressed onto the heat sink by means of low force pressure screws positioned at the edges. This is why much thicker layers (typically 100 μm…200 μm) of the poorly conducting thermal paste are needed. This problem becomes ever more critical the bigger the module is. In Figure 2, the four nests of the soldered DBC substrate are clearly visible. Sometimes attempts are made to reduce this bending using split base plates, where each DBC segment is allocated a separate base plate segment.

Figure 2. Measurement of PrimPack FF650R17IE4 base plate by Infineon

Despite the high thermal conductivity of the material (Cu: λ = 393 W/(m*K)) the base plate also accounts for a considerable share of the module thermal resistance due to its thickness (2.5...5 mm). Thinner base plates will only reduce this share to a limited extent, since the effect of reducing base plate thickness is decreased spreading of the temperature field and thus a reduction of the area through which the heat passes under the chips. Modules in the upper performance range (≥ 1000 A) use AlSiC base plates in conjunction with AlN ceramics. This is necessary in order to match the thermal expansion coefficients of the ceramic and base plate (α: AlN 5.7 ppm, AlSiC 7 ppm, Cu 17 ppm → reliability). The poorer thermal conductivity of AlSiC (λ = 180 W/(m*K)) compared to copper increases the thermal resistance, reducing heat spreading.

As mentioned a number of times before, omitting the base plate has proven to be the most effective way of eliminating the thermo-mechanical stress between base plate and ceramic, as well as bending. The lack of heat spreading in the copper material is partially compensated for by the eliminated resistances of base plate and rear soldering. Much more important, however, is that such layouts make a tighter seat of the chip on the heat sink possible. This permits a drastic reduction of the thermal paste layer to 20…30 μm. To this end, pressure elements press the DBC substrate onto the the heat sink at many points, close to the chips.

Figure 3. Problems arising through contact of power module to heat sink a) Module with base plate prior to assembly (base plate with convex bending) b) Module with base plate after assembly (highly exaggerated!) c) DBC module without base plate

Module insulation accounts for the biggest part of the internal thermal resistance. The alternative, however - for example external insulation by means of foil - would be even worse. Compared to today's standard type Al2O3 with a purity of 96% (thermal conductivity λ = 24 W/(m*K)), improvements can be achieved by using highly pure Al2O3 (λ = 28 W/(m*K)) or aluminium nitride (AlN, λ = 180…200 W/(m*K)), for example. The far better thermal conductivity of AIN reduces the module thermal resistance considerably, meaning that amperage ratings are higher. Unfortunately, this is true for the costs as well. The use of modules with improved thermal conductivity is often dispensed with for cost reasons. For this reason, AIN is largely preferred for modules with high insulation voltages (thicker insulating ceramics), since increased dielectric strength plus better thermal conductivity can be utilised at the same time.

Solder connections between chip and substrate - and (if applicable) substrate and base plate - also contribute a little to the thermal resistance. Omitting the base plate or replacing these layers by a thinner, sintered silver layer boasting better thermal conductivity could even half this share. The thermal resistance share for metal substrate areas depends mainly on the structure of the upper copper area, which is used as chip carrier and internal electrical connection system for the module. While the lateral heat flow in the copper substrate layer on the heat sink is virtually unaffected, heat spreading is limited by the geometric dimensions of the copper layers under the chips. For example, it was determined that for a 42 mm² chip on an Al2O3 DBC ceramic substrate, the value Rth(j-c) increases by around 15% if the copper area equals the chip area as compared with a case with unimpaired heat spreading.

The thermal resistance accounted for by the silicon chips increases in proportion to the thickness of the chips, which is determined by the forward blocking voltage and the chip technology. The size of the chip areas also determines the area through which the heat passes between chip and base plate or heat sink.

### Chip size effects

In accordance with the equation for thermal resistance, Rth should decline in inverse linear proportion to the chip area. In real layouts, however, an increase in the chip area-to-circumference ratio will reduce the relative temperature spread. If a chip sized 9 mm x 9 mm is divided into 9 segments, the inner segment with an edge length of 3 mm x 3 mm will have no room for heat spreading. This effect results in the dependency of the thermal resistance Rth(j-c) on the chip area A.

For high substrate thermal conductivity (e.g. AlN DBC), this effect is less marked. The poorer the heat conductivity of the ceramic substrate, the more marked the non-linearity of the Rth(j-c) dependency will become. This correlation also applies to the influence of module assembly on the heat sink, which is done using thermal paste or thermal foils. The relatively low thermal conductivity of λ = 0.8 W/m*K for this layer causes a thermal transient resistance Rth(c-s) between module base plate and heat sink. Besides the thickness d of the thermal paste layer, the relative share of Rth(c-s) in the thermal resistance Rth(j-s) between chip and heat sink will also rise if chip area is enlarged.

Figure 4. Rth(c-s) of a base plate module in relation to a single chip as a function of the chip area and thickness of the thermal paste layer for undisturbed heat spreading

Due to the heat spreading effect, the thermal resistance will only be reduced by 25% if the chip area is doubled (100 μm: 120 mm² = 0.235 K/W; 60 mm² = 0.315 K/W); according to the dimensioning equation for Rth, a 50% reduction would be expected. Figure 4 demonstrates the huge influence that optimum mounting technology has on thermal properties (thin thermal paste layer). This figure also shows that thermal limits prevent the use of bigger chips for enhanced power output. For this reason, the maximum chip sizes currently used in power modules are between 30 mm2 (IMS) and 150 mm2 (Al2O3 DBC). Higher power output can be reached by distributing heat sources (parallel connection of as many chips as possible).

### Thermal coupling

For the sake of small module geometry, more or less intensive chip thermal coupling has to be accepted if transistor and diode chips are to be positioned close to one another. An increase in the chip temperature caused by thermal coupling of heat flow, e.g. on Al2O3 DBC, can always be expected if distance a of the chips equals

$a = 0.6 \cdot \sqrt{A_{Ch}}$

For the example using 36 mm² chips in Figure 5, this would be true for a distance of 3.6 mm or above. This data may serve as a guideline, but depends on the heat spreading layers in the module in individual cases.

Figure 5. Thermal resistance Rth(j-s) of four 36 mm² chips as a function of the chip distance; (thermal paste thickness: with base plate 100 μm, without 25 μm), right: simulation of chip temperatures assuming same power loss and chip area but increasing distance (0 mm, 1 mm, 6 mm)

Depending on the closeness of the chips, thermal coupling will appear

• on the upper side of the DBC metallisation (e.g. fully equipped modules with maximum rated current in case class)
• over the base plate (e.g. IGBT + inverse diode of standard IGBT modules)
• over the heat sink

### Thermal impedance

As already mentioned above, in addition to the static behaviour of power modules, the dynamic thermal behaviour of power modules, which is charaterised by the thermal impedance Z th, is also of major importance. Figure 6 shows the development of thermal impedances Zth(j-c) over time for a module containing an Al2O3 DBC substrate for different chip areas.

Figure 6. Time curve of thermal impedances Z th(j-c) of a module with Al 2 O 3 DBC substrate for different chip areas

For the given module structure, the Zth curves for different chip areas may be shifted against one another, i.e. the absolute values will change in proportion to the chip area, however without influencing the time constants of the exponential functions. Consequently, thermal impedances for different chip areas, like thermal resistances, may be calculated in a given structure with the aid of the following equation:

$T_{th(j-c)^2} = Z_{th(j-c)1} \cdot \frac {R_{th(j-c)2}}{R_{th(j-c)1}}$

Thermal impedances of modules with or without a base plate are similar as long as heat build-up takes place inside the chip and the DBC substrate (Figure 7). For times > 100 ms, both curves differ over time. While the base plate module has thermal advantages in the time range up to 1…2 s owing to the heat storage capability of the copper plate, the module without base plate has advantages for longer periods owing to the reduced Rth value.

Figure 7. Comparison of thermal impedances of a 600 A / 1200 V module with base plates (SEMiX4) and without base plate (SKiiP4); reference point: drill hole in the heat sink 2 mm below the surface

Thermal Impedance and Thermal Resistance

Heat Transfer in Power Semiconductor Devices

Cooling Methods for Power Semiconductor Devices

Cooling Low Power Components

Heat Dissipation Using Cooling Plates

VN:F [1.9.17_1161]

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