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Posted on 01 June 2019

Heel Crack and Lead-Free Soldering

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Affecting Power Electronics Packages

Experimental and FEA study for the reliability of Al wire during IR reflow.

By Lunwen He, Shaohui Pan, LK.Wang and David Wei.Zhang Microelectronic Institute of Fudan University, 220 Handan Road, Shanghai, China and by S.S. Tey and Tiger Wu, Fairchild Semiconductor, Suzhou Corp, 1 Sutong Road, Suzhou, China

 

The D-PAK (JEDEC) power device is widely used in mobile electronic products and automotives because of its small footprint, low cost and compatibility with surface mounted technology (SMT). However, the aluminum wires commonly used in this package have small diameter and aluminum wire properties that make them subject to “heel crack,” one of the most complicated reliability problems in wire bonding. At the same time, the use of lead in electronic devices is becoming an increasing and serious concern for consumers and the manufacturing industry, many lead-free solders are now being used. But transferring to leadfree solders in reflow can lead to the changes of temperature hierarchy [1].

This article investigates the effects of solder IR reflow on heel crack, both in an experimental and FEA simulation study for the 2-5mil (diameter) aluminum wire. Its aim is to analyze the effect of solder reflow on the reliability of the heel region and to investigate the effect of a different temperature hierarchy to the heel region caused by leadfree solders.

Heel Crack

Heel crack is believed to be caused by the plastic strain at the heel region of the package induced by the wire bonding process and the coefficient of thermal expansion (CTE) mismatches between the leadframe, solder, Al wire, chip and electronic molding compound (EMC).

In our experiment, we use typical D-PAK (JEDEC) packages, each with the same wire bonding and other processes (die attach, molding, etc.) parameters. The aluminum wire used in the gate is 5 mil diameter. Table 1 shows the resistance between gate-tosource test results, which are divided into “low” and “high” categories.

Resistance between gate to source before reflow (unit O)

Since it is widely used in the surface mount technology, the samples undergo IR reflow under the peak reflow temperature of 220°C. Based on the real condition of the second level package, a three-time reflow procedure is chosen. The samples’ resistance between gate to source are obtained (Table 2). In the “low” category group, the resistance increases a little, about 0.7Ohm on average. But in the “high” group, eight of the ten samples experience a tremendous increase – 40 times larger than the original value on average.

Resistance between gate to source after reflow (unit Ohm)

As shown in Figure 1, six of the eight bonding-open products used experience the problem of heel crack at the gate pad of chip, causing increased resistance.

SEM shows the heel crack after decapsulation

Heel crack is the result of a) plastic strain at the heel region after wire bonding process (Figure 2), and b) stress and plastic strain caused by the CTE mismatches between Al, chip and EMC during the IR reflow. Based on these reasons, the plastic strain induced by a wire bonding process cannot be avoided in order to get a reliable bonding [7]. As the peak reflow temperature is larger than Glass transition temperature (Tg) of EMC, which is common at 170°C, the properties of EMC will significantly change below and beyond this point. The CTE is a case in point and the influence of EMC to the thermal stress and plastic strain distribution should not be ignored.

SEM shows the plastic strain caused by wire bonding

Our experiment is done at the temperature hierarchy of SnPb eutectic solder reflow. When transferring to lead-free solders, which can bring temperature hierarchy changes, especially a peak reflow temperature and wetting time increase[1], the problem will be worse.

3D Finite Element Model

According to the JEDEC standard of DPAK (Figure 3), the package size used here is about 9.98*6.54*2.3(mm), with 5mil aluminum wire applied as the gate wire. As the heel crack always happens at the gate pad are of the chip, the source wire, which is much larger than 5mil, is ignored.

D-PAK FEA model

Additional critical dimensional parameters in the model include the chip: 1.58*1.56*0.2(mm); die attach: 1.58*1.56*0.076(mm); and the leadframe dap: 5.33*3.84*0.51(mm). The wire loop and height are based on real conditions.

When referring to the material properties, it’s obvious that the whole process is non-linear and inelastic because of the thermal mechanics. Table 3 shows all material properties [8].

Material properties

In order to simplify our analysis, the residual stress induced by the first level package process is ignored, and the model is stress free at the reference temperature (300K). Owing to the good temperature uniformity during the IR reflow, it’s assumed that the temperatures applied on the model are the same. And, as the heel crack always happens at the chip pad bonding area, the platform is focused on this area.

Reflow Effecting Heel Crack

A Von mises stress and plastic strain comparison between the heel region and other area of wire with reflow temperature curve is shown in Figure 4. The stress distribution pattern shows that the stress at the heel region is much larger than other areas of the aluminum wire. The largest stress is located at the interface between the wire and the chip gate pad at heel region, which indicates micro crack is more possible to propagate at this point based on J-Integral.

Von mises stress distribution

From the stress and strain comparison results, it can be further defined that the heel region is subject to higher stress and plastic strain than other areas of the wire, because of the CTE mismatches between leadframe, die attach, Al wire, chip, and EMC. The terminations of joints are always predestinated for high stress concentration under stress conditions and plastic strain [7]. And actually during the wire bonding process, some plastic strain cannot be avoided at the heel region of the wire, so the fracture load at heel region is much less than in other areas. It can be proved that the broken area is always at the heel when carrying out the bonding pull test, which is used to estimate the wire bonding quality. In other words, the heel region is more subject to fracture during the reflow.

It’s obvious that the von mises stress decreases when the reflow temperature reaches 170°C of Tg, and the plastic strain keeps stable during the wetting time. After the wetting time, the stress starts to increase and the plastic strain decreases. This is because when temperature is below Tg, the CTE of EMC is 18 ppm/K, which is smaller than that of Al wire. Whereas when the temperature is above Tg, its value changes to 55 ppm/K, larger than that of Al wire. This property of EMC leads to the stress and plastic strain variations during wetting time. The material fatigue is mainly governed by the plastic strain and its repeatability, and this can give us a very good understanding of why there are so many heel crack samples after IR reflow occurs three times.

Besides von mises stress and plastic strain analysis, there is the shear stress and plastic strain. In fact, the shear stress also plays an important role during the fracture.

Different Reflow Temperature Hierarchy Effect

Owing to the world-wide drive for leadfree, reflow temperature hierarchy should be changed to meet the demand, especially the peak reflow temperature and wetting time. Besides 220°C peak reflow temperature, 240°C and 260°C peak reflow temperatures are applied in the simulation to investigate the influence of lead-free. Figure 5 shows the different reflow temperature comparison, and the results are described in Figures 6 and 7. Not only do the peak reflow temperatures change, but also the wetting time changes from 80s of 220°C to 100s of 240°C and 260°C [1].

Von mises stresses and plastic strains comparison of different peak reflow temperature at heel region.

The results show that both of the stress and plastic strain increase with the peak reflow temperature increasing. In fact, about 20% (0.004) plastic strain variation has been observed when the peak temperature changed from 220°C to 260°C. For many metals subjected to repetitive plastic deformation, a coffin-manson expression for the number of cycles to failure can be applied.

XZ shear stresses and plastic strains comparison of different peak reflow temperature at heel region.

Here is the plastic strain in the damaged region, and C1 and C2 are constants obtained from stress experiments, describes the life-time. Based on S.Ramminger’s theory [7] in the Al wire life-time model, C1=16.55 and C2=1.83, respectively. FIG.10 shows that the life-time decreases 28.4% after the peak reflow temperature shifting from 220°C to 260°C. This means that the peak reflow temperature and wetting time that correspond to lead-free solders have a great influence on the reliability of Al wire.

Life-time comparison of different peak reflow temperature

Upon analyzing the effect of solder IR reflow on the reliability of Al wire, as studied in both an experimental and FEA platform using a D-PAK, we find that the samples with higher resistance between gate to source confront 60% more heel cracks after three times IR reflow. This is caused by the plastic strain at the heel region induced by the wire bonding process and the CTE mismatches between leadframe, solder, Al wire, chip and EMC. These results indicate that solder IR reflow in the second-level package has a large influence on the heel region of Al wire.

The FEA platform is further extended with respect to fracture mechanics and effects of different reflow temperature hierarchies on the heel region for lead-free solders. We conclude that the max stress and plastic strain located at the interface between the wire and the chip at the heel region, and with the temperature varied from 220°C to 260°C, the plastic strain increases about 20%, which is critical for material fatigue. Based on coffin-manson aluminum wire lifttime models, its life-time would decrease by 28.4%.

 

References:

1) C. Michael Gamer, Vivek Gupta, and Vivek Bissessur, et al., Intel Corporation, “Challenges in Converting to Lead-free Electronics”, Electronics Packaging Technology Conference, 2000.
2) R.L. Shook and V.S. Sastry, Lucent Technologies, “Inflluence of Preheat and Maximum Temperature of the Solder-Reflow Profile on Moisture Sensitive IC’s”, Electronics Packaging Technology Conference, 1997.
3) Yizhe Elisa Huang, Debbie Hagen, and Glenn Dody, et al., “Effect of Solder Reflow Temperature Profile On Plastic Package Delamination”, IEEWCPMT Int'l Electronics Manufacturing Technology Symposium, 1998.
4) Zhenwei Hou, Guoyun Tian, and Casey Hatcher, et al., “Lead-Free Solder Flip Chipon-Laminate Assembly and Reliability”, IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 24, NO. 4, OCTOBER 2001.
5) Chunyan Yin, and Hua Lu, et al., “Effects of Solder Reflow on the Reliability of Flip-Chip on Flex Interconnections Using Anisotropic Conductive Adhesives”, IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 27, NO. 4, OCTOBER 2004.
6) T.Y. Lin *, C.M. Fang, and Y.F. Yao, et al., “Development of the green plastic encapsulation for high density wirebonded leaded packages”, Microelectronics Reliability 43, 2003, pp. 811–817.
7) S.Ramminger, N.Seliger, and G.Wachutka, “Reliability Model for Al Wire Bonds subjected to Heel Crack Failures”, Microelectronics Reliability, 2000.
8) Yong Liu, Scott Irving, and Mark Rioux, et al., “Die attach delamination characterization modeling for SOIC package”, Proc Electronic Components and Technology Conference, 2002.

 

 

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