Posted on 29 June 2019

High Efficient Power Converter for Low Voltage Traction Applications with Power Multiplication

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A combined optimization of MOSFET parameters, electro-thermal concept and gate drive control is the key

In low voltage battery fed drives, such as in lift trucks and electrical passenger cars, power MOSFETs with high current ratings up to approximately 100 to 200 ampere and the converter design play a significant role with respect to the performance and efficiency of the converter drive. Due to the limited installation space in automotive applications, packaging and efficiency are major points of interest in the development of power converters. In this article a three phase 24 V / 5 - 15 kVA dc/ac inverter concept based on two paralleled, special molded power MOSFET modules is presented, which has been developed by the Competence Centre of Power Electronics Schleswig Holstein, Germany.

By Ole Mühlfeld, Björn Wittig and Friedrich W. Fuchs, Christian-Albrechts-University of Kiel and Jacek Rudzki Danfoss, Silicon Power GmbH


Typical applications of low voltage power MOSFETs are dc/ac inverters and dc/dc converters, e.g. for feeding a three phase ac motor or for the use in battery backup systems. Due to the high power demands and low dc-link voltages of, e.g. 24 V or 48 V, high currents result. Thus there is an intensive demand for low voltage power MOSFETs with a low drain-source on-state resistance RDS(on) on the market to achieve lower conduction losses at several hundreds of amperes of load current. This request in mind, a 24 V / 5 kVA dc/ac inverter concept based on molded power MOSFET modules and without active cooling is developed. Additionally a power multiplication, where up to three discrete 5 kVA inverters are connected in parallel, has to be possible to achieve an output power of, for example, 15 kVA.

Thus a power MOSFET with a very low drain-source on-state resistance RDS(on) of typical 0.72 mΩ @ TJ=25°C was developed by Fraunhofer Institute for Silicon Technology which fulfills these requirements. Besides the gate to source threshold voltage VGS,th is about 4.4 V to achieve higher robustness against parasitic turn-on. These power MOSFETs are included in the power module, depicted in Figure 1.

Power MOSFET module with integrated three phase full bridge inverter topology

To accomplish a passive cooling of the dc/ac power system two MOSFET devices have to be connected in parallel for each bridge to handle load currents up to 250 Arms. Besides the characteristic and performance of the semiconductors one focus has to be on the power module design. A small and flat molded power module is essential for compact inverter dimensions but also a low thermal contact resistance is desirable, which has been accomplished with the molded module, depicted in Figure 1, by a thermal resistance of Rth,JC = 0,107 K/W. The final module measures 61 mm x 49 mm x 5 mm (without connectors).

In terms of reducing the size of the module and increasing the reliability, two new technologies are applied: molding and sintering. Commonly power electronic modules are filled with silicone gel to assure a resistant layer against outer environment influences like humidity and provide electrical insulation. Replacing silicone gel with mold compound provides a reduced volume of the power module and additionally allows increasing the temperature operating range.

One of the main challenges in the power electronic packaging is to substitute the solder by other more reliable materials. Silver powder can be applied instead of solder layer between die and substrate to increase the melting point up to 960°C. This assures more reliable joining layer even for elevated operating temperature. Additionally the better thermal property of the silver layer allows decreasing the junction temperature TJ of the die, thus enhancing the life time of the power modules.

Due to the demand for high efficiency and low EMI emissions the optimization of the stray inductance of the commutation path in the two paralleled power modules is of high interest. According to the well known formula Uind=Lσ•dI/dt the reduction of the switching loop inductance allows to use shorter switching times, while the amount of induced overvoltage stays constant. This has two advantages regarding the losses. The switching losses decrease with faster current transitions and the on state losses of the power semiconductor decrease when lower breakdown voltages are sufficient. Hence, the direct result of the lower stray inductance is a higher efficiency of the overall system.

An analysis and optimization of the parasitic inductances of the power modules and the busbars has been performed aided by simulations using the PEEC method. In this work, 10 different DCB layouts have been investigated and compared regarding their stray inductance. Based on the results an optimization of the best suited DCB layout was performed and fabricated in a small sample series afterwards (Figure 1).

One newly designed feature of the presented inverter is the combined use of two independent busbar systems (Figure 2). The common planar busbar system allows easy connection of power cables. A desirable multiplication of the output power (e.g. 10 kVA or 15 kVA) can simply be done by paralleling the inverters via the screwable copper plating, which is illustrated in Figure 3. Because of the low maximum pwm signal propagation delay time variations of the gate driver below 68 ns and the low device variation of the RDS(on), there is no essential measurable splitting of the load current between two paralleled power MOSFETs or power modules during switching or on-state.

Construction scheme of the passive cooled three phase 24 V / 5 kVA dc/ac inverter

Three paralleled 5kVA inverters for output power multiplication up to 15 kVA

A second vertical busbar system ensures the electric connection between the power module and the dc link capacitors as well as the gate drive circuit. The cross-section of the busbars was chosen to ensure acceptable low conduction losses and to ensure low stray inductance.

This approach allows to exclude the planar busbar from the commutation path, which is formed by the vertical busbars between the power modules and the dc link capacitors. The chosen arrangement of the phases in the power modules leads to an antiparallel current flow in the vertical leads. Thereby the magnetic mutual coupling in the vertical busbar is increased leading to a reduction of the overall stray inductance. Compared to single leads without coupling effects, the inductance of the single commutation path could be reduced from 38 nH to 25 nH. Through the parallel operation of two modules this value is reduced to the half (13 nH) during conventional operation.

In Figure 2 the construction scheme of the presented 24 V / 5 kVA dc/ac inverter is shown. Here the power modules are mounted on a heat spreader. The power ports are connected via a busbar on top of the modules. Above this planar busbar the gate drive circuit board including the dc link is arranged and is being electrical connected via signal and power leads.

The use of these additional vertical leads has been necessary because thermal simulations have shown that the heat transfer from the power modules to the driving circuit and the dc link capacitors has to be reduced in order to guarantee reliable operation of the inverter and to increase lifetime of the capacitors.

Additionally, the dc link capacitors are effectively cooled by a second heat sink on the top of the inverter (not shown in Figure 2).

Due to the unavoidable stray inductances in the switching loop path and the high load currents there has to be paid special attention to the design of the gate drive circuit. At turn-on during the current rise time the induced voltages at the stray inductances lead to an enormous lower drain to source voltage stress at the power MOSFETs and therefore to lower switching losses. In contrast to that at turn-off these induced voltages generate an overvoltage at the device during the whole current fall time. Therefore turn-off energies of low voltage power MOSFETs are several times higher than the turn-on energies at high load currents. Designing the gate drive circuit, there has to be found a compromise between switching the device as fast as possible to reduce switching energies and delay times and to keep the device in its safe operating area below a limit of permitted overvoltage. For this reason a du/dt-control has been implemented on the gate driver which leads to about 25% lower switching losses and more than 50% lower turn-on and turn-off delay times compared to a conventional gate drive circuit with just a gate resistance at the same induced overvoltage.

Switching the device as fast as possible to reduce switching energies and delay times and to keep the device in its safe operating area

The inverter was fabricated in a small sample series after the phase of design and tested in the laboratory afterwards. A type test has shown the capability of delivering the rated output power, keeping the temperatures within the limits given by the specifications. The efficiency is 97.4% at nominal operation of 2.9 kVA. Besides, a longterm test was started and is ongoing at the moment.


Within a combined project between universities, a research institution and industrial partners a 24 V / 5-15 kVA inverter concept and prototype was developed. Among the special features are the compact size, high efficiency the sufficiency of passive cooling and the possibility for parallel operation of multiple inverters.

These features where obtained by usage of a newly developed components like a new power semiconductor, an adapted power module, an optimized power section design and a state-of the art driving circuit which are briefly presented in this article.

The test of the fabricated prototypes shows accordance to the design targets defined at the beginning of the project. Investigations on the lifetime estimation and reliability are ongoing.


This project was accomplished by the ‘Competence Centre of Power Electronics Schleswig-Holstein, Germany’ Members of the project: Jungheinrich Norderstedt AG ESW GmbH Danfoss Silicon Power GmbH Fraunhofer Institute for Silicon Technology Westcoast University of Applied Sciences, Germany University of Applied Sciences Kiel, and Germany Christian-Albrechts-University of Kiel, Germany.



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