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Posted on 26 September 2019

High Reliability for 1200V High Voltage Integrated Circuit for Half Bridge Applications

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Reduce the IC’s supply current for about 50%

This article presents a high reliability 1200V High Voltage Integrated Circuit (1200V HVIC) for half bridge driver applications. It is suitable to drive Power MOSFET/IGBT module in industrial inverter systems. The pin configurations and the functions are compatible with the previous 1200V HVIC, where high reliability is achieved by high switching noise immunity realized by using a new process and protection circuits.

By Masahiro Yamamoto, Liang Xiaoguang, Manabu Yoshino, Takanobu Takeuchi and You Habu, Power Device Works, Mitsubishi Electric Corporation, Japan, and Marco Honsberg, Mitsubishi Electric Europe B.V., Germany

As the inverter system market for industrial purposes grows motivated by the energy saving trend, the demand of IGBT module driver for motor drives is increasing. MOSFET/IGBT modules in AC 400V inverter systems require high reliability of a 1200V HVIC driver, because the operating condition is severe under the various switching noises. Mitsubishi Electric Corporation released a 1200V HVIC (M81019FP) in 2005 [1]. A new 1200V HVIC (M81738FP) has now been developed applying the 2nd Generation Divided RESURF structure. It has evolved from the previous 1200V HVIC (M81019FP) [2] [3], and is pin- and package compatible with the M81019FP.

Technologies for High Reliabilities

High latch-up immunity by utilization of a new 1200V HIC process

A Cross-sectional view of 1200V Nch-LDMOS applying the 2nd Generation Dividded Surf Structure, and a top view of a PolyRFP

As shown in Figure 1, the main different features between the new process structure and the conventional process are P-epi/P-substrate, N+ buried layer and high resistivity Polycrystalline silicon Resistor Field Plate ‘PolyRFP” [2]. Figure 1 shows a top view of a PolyRFP around the high voltage region [2]. The high resistivity Poly- Silicon area shaped like a spiral connects the high voltage electrode to the low voltage electrode on the RESURF Isolation Region. Furthermore, it relaxes the surface electric field effectively more than the conventional Multiple Floating Field Plate “MFFP”. Thus it achieves a break-down voltage above 1200V as shown in Figure 2.

A breakdown voltage of M81738FP (high side circuit)

The conventional process structure is the 1st Generation Divided RESURF Structure which has a deep N well diffusion layer in the Psubstrate [4]. Since the deep N well diffusion layer has a very high impedance, switching noise may cause a latch-up by the activation of the parasitic PNP transistor. Therefore, the CMOS transistors in the chip are placed with a distance to each other in order to prevent a latch-up. As a consequence of this distance requirement the chip size had to be enlarged respecting the applied design rule. The 2nd Generation Divided RESURF Structure indicates the N+ buried layer with-in the Pepi / P-substrate as shown in Figure 1. The N+ buried layer impedance is lower than the N diffusion layer achieving a high latch-up immunity [2]. A parasitic PNP transistor action is generally caused by a transient current (which for example is caused by the noise from the power supply) which flows through the N diffusion layer. However, the N+ buried layer, which is shown as RN+ in Figure 3, can prevent this action, because the low voltage which occurs in the RN+ (low impedance) does not reach the threshold voltage of the parasitic PNP transistor. Thus the new 1200V HVIC process pattern layout now allows to approximating the CMOS transistors to each other maintaining a high latch-up immunity. In addition, the CMOS transistors themselves were shrunk. Figure 4 shows the chip photographs of both M81738FP and M81019FP. The M81738FP’s chip size is the half size of the M81019FP’s chip. The new 1200V HVIC process realized both, high latch-up immunity and shrunk chip size.

N+ buried layer of the 2nd Generation Divided RESURF structure in low side circuit and the equivalent circuit

Chip photos of the 1st generation ( A left) and the latest generation of 1200V HVIC ( B right)

High immunity to power supply surges

Using a shrink wafer process may reduce the immunity to switching noise originating from the power supply during operation.

Functional block diagram of M81738FP

Active supply clamp circuit diagram

Figure 5 shows the M81738FP’s functional block diagram that reveals an active power supply clamping circuit to protect the other internal circuits from the power supply surges which are generated by switching noise.

Figure 6 shows that this active clamp circuit is composed of the CMOS transistor output, which absorbs the surge energy, and the power supply voltage detection circuit.

When a power supply surge occurs exceeding the threshold voltage of the detection circuit, the CMOS transistor output is turned-on. Hence the CMOS transistor absorbs the surge energy and prevents that the other internal circuits would be destroyed.

The performance of the active clamp circuit depends on the transistor size of the CMOS transistor output. If the CMOS transistor size is large, the active clamp circuit performance is higher. But that means that the high performance causes a large chip size. However the CMOS transistor output size of M81738FP is optimized between the chip size and the performance requirements based on several evaluation results. As a conclusion Figure 7 shows that M81738FP achieves higher performance and more safety margin than the previous 1200V HVIC (M81019FP).

Destruction toughness at Vcc node

High immunity to Vs minus undershoot noise

Figure 8 shows typical connection diagram of a half bridge application circuit. In the switching action, when the high side transistor Q1 is turned-off, the inductive load causes the current (IFW) to keep on flowing. Therefore, because the current (IFW) flows through the parasitic inductance L3-L4 and the FWDi of Q2, a transient Vs minus undershoot peak occurs at the Vs node. This peak may lead to two problems which are the HVIC destruction at worst case or a wrong signal at the HO output.

Typical connection diagram of a half bridge application circuit

However, the M81738FP has got a high immunity to Vs undershoot. Figure 9 shows the turn-off waveforms of a DIPCIBTM which is driven by a M81738FP [1]. Thus no destruction and no wrong function occurred even at 3 times the Ic rating.

Waveforms of DIPCIB™ during turn-off

Compatibility with the previous industrial standard 1200V HVIC model M81019FP It is easy to substitute the previous 1200V HVIC model (M81019FP) with this latest generation product (M81738FP), because they are pin- and package compatible to each other. The product’s pin configurations and functions are the same as those of the M81019FP.

Future developments

This new shrink process which is applied to M81738FP has several potentials to benefit to the inverter system. The M81738FP’s propagation delay is designed to be equal to that of the M81019FP by using delay circuits. However, the circuit operation speed of the new shrink process is 2 times faster than that of the conventional process. Next new 1200V HVICs will be able to realize a short propagation delay contributing to reduce the dead time. Thus the reduced dead time will provide an advantage to the inverter’s control system design.

Another potential is the reduction of the power supply current. It will be possible to reduce the IC’s supply current for about 50% more than the M81738FP today. More potential is realized by a laser trimming technique which equalizes the lot by lot performance deviations. Such an optimization can be employed e.g. for the threshold level linked to the current detection level of the short circuit protection circuitry.

Literature

[1] Marco Honsberg, et al., Proc. of PCIM2005, pp.461-468, (2005).

[2] M. Yoshino et al., Proc. of ISPSD’10, pp.93-96., (2010)

[3] K. Shimizu and T. Terashima, ‘The 2nd Generation divided RESURF structure for High Voltage ICs’, Proc. ISPSD, 2008,pp.311-314.

[4] T. Terashima, K. Shimizu and S. Hine: ‘A new Level-shifting Technique by divided RESURF structure’, Proc. ISPSD, 1997, pp.57-60.

 

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