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Posted on 14 December 2019

IGBT Technologies

 

 

 

 

 

 

 

Below is an outline of several IGBT technologies that are in common use in the field of power electronics.

PT concept

The first "Punch Through" (PT) concept, which is still used today as a result of continuous developments, uses a p+ substrate as a base material and n+ and n- regions applied by means of epitaxy. Today, PT-IGBTs can also have a trench-gate structure. In forward off-state, the space charge region comprises the entire n- region. In order to keep the epitaxy layer as thin as possible even for high blocking voltages, the field at the end of the n- drift area is reduced by a highly doped n+ buffer region.

PT-IGBTs have a high emitter efficiency for holes in the p+ layer drifting into the n- drift area because the substrate is relatively thick and highly doped. The PNP current gain has to be reduced via the base transport factor (n- drift area, n+ buffer), which is achieved by reducing the charge carrier lifetime in the n+ layer by increasing the recombination centers (e.g. gold doping or electron beam radiation). The hole current amounts to 40...45% of the total current.

NPT concept

The basis of " Non Punch Through" (NPT) IGBTs, which were soon introduced by numerous manufacturers, is a thin, weakly doped n- wafer; the collector side p+ zone is created by way of back implantation. Here, the n- drift area is so wide that in forward off-state, the electric field is fully depleted in the n- drift area up to the maximum permissible off-state voltage and cannot – in contrast to the PT concept – spread over the entire n- region.

NPT-IGBTs have a very thin collector side p+ emitter region, which results in a low emitter efficiency (γE = 0.5) of the PNP subtransistor - it is not necessary to lower the base transport factor by reducing charge carrier life time. The hole current amounts to 20...25% of the total current. In contrast to PT-IGBTs, the saturation voltage of NPT-IGBTs has a positive temperature coefficient, improving both the current symmetry between the cells in single chips and between chips connected in parallel. Switching times for hard switching are comparatively shorter and less dependent on temperature; overcurrents can be better cut off as a result of improved internal current limiting.

SPT and SPT+ concept

The "Soft Punch Through" (SPT) IGBTs by ABB is a further development of the NPT concept. Here, too, the base material is a thin, weakly doped n- wafer; the p+ region at the collector is generated by back implantation. Here, an additional p+ region has been implanted as a field stop layer above the collector n+ region. This reduces the thickness of the drift area – like the highly doped n+ buffer layer in the PT-concept – by diminishing the electric field at the end of the n- drift area in front of the collector region. Since this layer need not curb the high emitter efficiency as is the case in the PT-IGBT, but has to reduce the field intensity only, it is less highly doped than the n+ buffer of the PT-IGBT.

With the same forward off-state voltage, the thickness wB of the n- drift area can be significantly reduced in comparison to an NPT-IGBT; this also considerably cuts the on-state voltage (~ wB ) of the drift area. The positive temperature coefficient of the on-state voltage and the high component ruggedness are maintained.

The next development, known as SPT+, contains additional n regions which are arranged in the n- drift area around the p channel areas, so that they can impede the drain of minority carriers in the on-state (hole barrier). This increases the charge carrier density in on-state in order to reduce the on-state voltage without significantly impairing the switching behaviour. At the n- /n junction between drift area and additional n region, a diffusion voltage of approximately 0.17 V will occur, preventing hole drain (hole barrier). In order to produce neutrality, electrons continue to be supplied from the channel area; the concentration of free charge carriers increases.

Structure of an SPT+ IGBT, Effect of hole barrier

Figure 1. a) Structure of an SPT+ IGBT, b) Effect of the hole barrier

NPT concept with field stop layer and trench-gate structure

For these very common IGBT chips, a field stop layer was added to the NPT concept and the planar gate was replaced by a vertical trench-gate structure.

The basis here continues to be a thin, weakly doped n- wafer into which an additional n+ region has been implanted as a field stop layer on the back above the p+ region of the collector. This reduces the thickness of the drift area – like the highly doped n+ buffer layer in the PT-concept – by diminishing the electric field at the end of the n- drift area in front of the collector region. Since this layer need not curb the high emitter efficiency as is the case in the PT-IGBT, but has to reduce the field intensity only, it is less highly doped than the n+ buffer of the PT-IGBT.

With the same forward off-state voltage, the thickness wB of the n- drift area can be significantly reduced in comparison to an NPT-IGBT; this also considerably cuts the on-state voltage (~ wB ) of the drift area. The positive temperature coefficient of the on-state voltage and the high component ruggedness are maintained. During turn-off, the tail current is initially somewhat higher than for an IGBT without field stop layer, but then it drops faster.

The vertical gate arrangement in the shape of a trench inside every IGBT cell allows for a vertical channel track in the p well. Since the active silicon area is enlarged, better control of the channel cross-section is possible and thus a lower channel resistance can be obtained. For a given silicon area, the cell area can be reduced even further. This is why higher current densities, lower forward losses, a higher latch-up strength, lower switching losses, and higher breakdown voltages can be obtained than in IGBT with planar gate structures.

In the IGBT4 generation from Infineon, cell pitch (i.e. the distance between the gates of neighbouring cells) was further reduced compared to its predecessor generation IGBT3, meaning that the cells were shrunk in size. Cell optimisation and chip thickness reduction has helped to improve the static and dynamic properties. However, smaller chips also mean a higher thermal contact resistance Rth(j-c) or Rth(j-s) . The performance increase achieved in comparison to the IGBT3 therefore largely results from the higher permissible chip temperature of 175°C as compared with 150°C for IGBT3.

CSTBT concept

In these IGBTs, which were formerly also known as Injection Enhanced Gated Transistors (IEGT), the charge carrier injection among the n-emitters is increased by a "hole barrier", as described for the SPT+ concept. The additional n-doped region is inside the trench-gate structure below the p-base areas. Positive charge carriers are enhanced below the hole barriers, which results in an effective resupply of electrons from the channel and thus a local increase in free charge carrier concentration.

Plugged cells

Rather than bonding individual trench cells, but short-circuiting the polysilicon in the gate area with the emitter metallisation instead (plugged cells), a further improvement in IGBT features can be achieved. Increasing the cell spacing and reducing the p areas increases charge carrier concentration at the emitter, affecting the on-state voltage to a greater extent than the increased voltage drop over the channel area as a result. Another advantage of plugged cells is the lower collector current in the event of a short circuit as compared to conventional Trench-IGBTs.

RC-IGBT

Reverse-conducting IGBT chips which can be loaded with the same current density in IGBT and diode mode are known as Reverse Conducting IGBTs (RC-IGBT). The aim is to reduce the use of anti-parallel freewheeling diode chips (hybrid connected in the module), which has the following advantages:

  • Improved performance per module area
  • Increased overload capability (surge withstand strength)
  • Improved parallel switching capability
  • Increased R th(j-c) diode/IGBT ratio
  • Reduction in temperature ripples per chip
  • Improved flexibility for optimal thermal properties in power module

Structure of an RC-IGBT

Figure 2. Structure of an RC-IGBT

Hole injection from the p+ collector region into the IGBT section also has to be performed when voltages and currents are low. Various structural measures help to attain low turn-off losses and soft recovery behaviour in the diode across the entire temperature range; IGBT latch-up is prevented. For this purpose, it is necessary to set very precise doping profiles for the p-emitter regions and the p+ /n+ collector regions. The cells are thus not designed with highly doped p+ regions but a fine structure of p regions in order to obtain a lower injection efficiency. Local control of the p charge carriers by means of implantation or proton irradiation allows for diode turn-off losses to be reduced without affecting the blocking voltage and the IGBT losses too much. Another way of reducing diode turn-off losses is to introduce a MOS-controlled diode ( Bimode Insulated Gate Transistor BIGT).

 

For more information, please read:

Criteria for Successful Selection of IGBT and MOSFET Modules

Teaching Tool for IGBTs and Thyristors

I²t of IGBT and Other Power Transistor Circuits

 

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