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Posted on 02 August 2019

Increasing IGBT Inverter Power Density

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High-temperature capable and low-inductive design

Increasing the power density is a key development factor for power electronic inverter systems. On IGBT chip level the current density was increased by a factor of three in the last 22 years. Progress in the IGBT technology and the utilization of new materials like silicon carbide and gallium nitride will allow more current per mm² in the near future by improved switching performance and higher maximum operation temperature TVJ_MAX. This trend leads to a higher relevance of the system inductance; that can be a limiting factor concerning the maximum switchable current.

By Klaus Vogel, Infineon Technologies AG, Warstein, Germany

 

Increased IGBT operation temperature

An increase of the IGBT operation temperature TVJ of today’s 150°C at IGBT 4 to 175°C at IGBT 5 allows increased power dissipation and a higher amount of switching current per device. This can bring inverter designs with high parasitic inductance to the limit concerning overvoltage peak and oscillations during turn-off. The occurring IGBT collector overvoltage is caused by the stray inductance Lσ and the current slope di/dt. This relation is described by the equation:

Equation 1

The current shape is also dependent on the applied voltage between collector and emitter. Higher voltage applied to the IGBT during turn-off causes an earlier removal of charges from the device and the tail current disappears [1]. This means that the parasitic inductance that causes an overvoltage in turn accelerates the current fall and this again causes a higher over-voltage. In addition, high di/dt and Lσ can lead to oscillations that cause electromagnetic interference (EMI). This is a consequence of exciting a resonant circuit, consisting of the parasitic inductance in the commutation loop and the chip capacitance, by the high frequency components of current and voltage.

Increased current ratings, though, require reduced stray inductance of the commutation loop in total in order to avoid serious problems with voltage and EMI requirements. This requirement may be summarized by the simple constraint LσI = constant [1]. If the stray inductance can be reduced to a minimum the switching silicon can be optimized for higher turn-off speed and consequently lower turn-off energy losses. The increase of power losses at turn-on due to lower parasitic inductances [2], [3] has to be compensated with chips having faster turn-on behavior and freewheeling diodes with lower reverse recovery charge.

Low inductive and high temperature capable inverter setup

In the following chapters a new system design will be introduced and compared with a typical 3-phase system with 62mm modules, about 70nH system inductance and a power density of 8kVA/l. The reference inverter stack (6PS0400R12KE3-3F-C4V with FF450R12KE4 modules) is designed with electrolyte DC-Link capacitors, bus bar with strip line geometry and air cooled heat sink. All devices are interconnected with screws; at this point the strip line geometry is interrupted.

The optimum way to reduce the system inductance as much as possible is to keep a strip line structure in the whole system of capacitors, bus bar and module [1]. This is unfortunately not possible with today`s usual devices due to intersectional screw connections caused by the interfaces between the capacitors respectively the power modules and the DC bus bar. These interruptions result in segments with geometry like two-wire connectors and lead to a dominating effect regarding the inductance. For this study a new system design with prototype devices has been designed and the benefits have been evaluated.

The newly developed power module [1] follows the strip line concept, using the principle of a laminar layout and multiple connection points in an interleaved structure to minimize the total system inductance. To contact the module, the proven PressFIT technology [4] of Infineon was used. Arranging pins in a line-wise way allows a very lowinductive and low-resistive connection to the rest of the system. Furthermore this technology has an advantage at high temperature cycling application regarding lifetime compared to solder joint technique [4]. To work with IGBT 5 at TVJ_MAX of 175°C without lifetime restriction the prototype module is based on Infineon`s new .XT technology [5] [6] [7].

Following the idea of avoiding bolt connections [1] a prototype DCLink capacitor in power capacitor chip (PCC) [8], [9] concept with Infineon` s PressFIT contact has been provided by the company Epcos. The PCC concept has a very low equivalent series inductance (ESL) and low equivalent series resistance (ESR) allowing a high capacitor current per volume. Due to the high voltage capability [8] no series connection of capacitors is necessary. Furthermore this type of device is improved regarding maximum ambient temperature and lifetime compared to electrolyte technology [8], [9].

To interconnect the above mentioned devices a high current PCB with a maximum operation temperature of 150°C and 800μm copper per pole was chosen. This allows a continuous strip line design in the whole power electronic system. The IGBT driver circuit is positioned mechanically decoupled from the power part of the stack. Converting the study in [5], that evaluated the consequence of an operation at TVJ of 175°, to the worst case ambient temperature of the reference stack a maximum temperature of 90°C on the PCB is expected. Infineon’s IGBT driver 2ED020I12FA allows a maximum ambient temperature of 125°C and was chosen to control the IGBTs.

Figure 1 shows the module prototype and the whole inverter system.

Left side, low inductive IGBT half bridge module prototype

Overall, all measures result in a system inductance below 10nH, about 60nH lower than the reference stack. The effect in the turn-off behavior using fast IGBT 3 1200V chips at nominal conditions by different stray inductance values can be seen in figure 2.

Figure 2a depicts the switching behavior of a FF400R12KT3, a 62mm module with IGBT3 fast technology. It is visible, that with a stray inductance of 70nH the fast IGBT3 chip tends to oscillate. The overvoltage is 280V. By reducing the stray inductance to 35nH – figure 2b – respectively with the new low-inductive module to 10nH – figure 2c - the overvoltage is reduced down to 160V respectively 80V. No oscillation occurs in the 10nH setup. The current falls with softer tail due to the lower overvoltage compared to the system with higher inductance.

Different switching behavior by different parasitic inductance

This low-inductive setup allows the use of faster switching IGBT 5 with higher current carrying capability and reduced power losses.

Increased inverter output power

Having reduced the system’s commutation inductance to a value of less than 10nH, increased current and power densities enabled by increased junction temperatures may easily be handled. Moreover, even fast switching devices comprising reduced power losses may be implemented without coming into trouble with overvoltage and softness restrictions. An oscilloscope picture of the turn-off event at 1200A - two times the module nominal current - and increased DC-Link voltage of 800V in the low inductive system is depicted in figure 3.

Fast IGBT 5 turn-off at 1200A - two times module nominal current

It is visible that the fast IGBT 5 at overload condition has still enough tail current, the overvoltage peak has a value of 1090V and no oscillation is visible. A further optimization step on the chip design regarding lower tail current and consequently lower turn off losses is possible.

Figure 4 shows a comparison of the relation between IGBT junction temperatures and output current of the reference stack with IGBT E3 and E4 versus the low inductive prototype with fast IGBT 5 chips and Tvj_max of 175°C.

Relation between IGBT junction temperatures and stack inverter output current

It is clear that the new design allows an increase of the output current by 18% as compared to IGBT 4 at TVJ 150°C. The increase of the maximum junction temperature to 175°C result in 40% more current as compared to IGBT 4. The low inductive and high temperature capable stack converter achieved a power density of about 14kVA/l. Beside this, care must be taken regarding the temperature raise seen at other system components to guarantee that the frequency inverter` s lifetime does not suffer from an elevated temperature.

Conclusion

The increase of the maximum operation temperature leads to higher current capability per chip area. This can bring inverter designs with high parasitic inductance to the limit concerning overvoltage peak and oscillations during turn-off. The application of fast IGBT chips at higher current is only possible with low-inductive module and system design. This is a door opener and requirement for the application of other fast chips like SiC JFET with reduced electrical magnetic interference and lower overvoltage peaks.

The study shows that the usage of chips with optimized energy losses and higher operation temperature resulted in circa 50% higher power density compared to a reference stack with today’s state of the art technology. An advance step is possible through further tuning of the IGBT chip design or usage of new die technologies.

 

References:

1) Dr. R. Bayerer et al: Power Circuit design for clean switching, CIPS 2010, Nuremberg, Germany.
2) M.Bäßler et al: On the loss - softness trade-off: Are different chip versions needed for softness improvement?, PCIM 2009, Nuremberg, Germany.
3) W. Rusche et al: Influence of Stray Inductance on High-Efficiency IGBT Based Inverter Designs, Issue 7, 2010, Power Electronics´Europe.
4) M. Thoben et al: Press-Fit Technology, a Solderless Method for Mounting Power Modules, PCIM 2005, Nuremberg, Germany.
5) K. Vogel et al: IGBT with higher operation temperature - Power density, lifetime and impact on inverter design, PCIM 2011, Nuremberg, Germany.
6) A. Ciliox et al: New module generation for higher lifetime, PCIM 2010, Nuremberg, Germany.
7) K. Guth et al: New assembly and interconnects beyond sintering methods, PCIM 2010, Nuremberg, Germany.
8) Harald Vetter: Mission- Profile bezogene PCC- Designs zur Integration in HEV- Converter, AUTOMOBIL-ELEKTRONIK 6/2007.
9) Harald Vetter: Zwischenspeicher für Hybride, AUTOMOBILELEKTRONIK_ Dezember 2007.

 

 

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