Semiconductor parameter variation, parasitic elements and mechanical construction influence the dynamic behaviour of parallel connected IGBT. The effects are demonstrated with a combination of measurements and simulations in intentional unbalanced setting of a test circuit. Theoretical worst case considerations of parameter variation are set in relation to measured parameter distribution from production tests and the probability of the existence of such devices.
To achieve high inverter power and currents a parallel operation of power semiconductors is necessary. Objects of interest regarding to the switching behaviour are at chip level where several chips performing as one switch in a module (see Fig. 1) or at the module level where several modules in parallel are used as one inverter leg.
Figure 1. Parallel connection of IGBT and Diode chips inside of a power module
For a reliable and economic operation one design goal is a similar junction temperature for all parallel units. To reach this a similar power dissipation caused by a good current sharing between the parallel units is necessary. Uncertainties according this topic results in the everlasting questions: Is for a parallel operation a current de-rating necessary and how much is it for this special kind of devices and application? The distribution of the overall losses is influenced by
• differences in current sharing because of a variation of static parameters (e.g. forward voltage of semiconductors, different length of terminals and interconnections);
• different temperatures and its effect on the semiconductor parameter (temperature coefficients), caused by different power dissipation itself or by a different position at the heatsink in the heat flow;
• differences in switching behaviour because of differences in the semiconductor parameter an in the mechanical construction.
The first topic was object of a previous paper /1/. There it was pointed out, if 6 chips used from upper and lower specification limit (USL and LSL) in parallel, then a de-rating of 50% would be necessary theoretically. It becomes worse with more chips. But with a statistical approach and an acceptable probability of 1ppm the maximum de-rating is reached for 3...4 chips in parallel with 10% and for a higher number the de-rating decreases again.
The second topic is especially for large systems critical to find a solution with equal cooling conditions for al elements. A simple but graphic example of the temperature influence can be found in the Interactive Power Electronic Seminar /2/ for a parallel connection of two diodes.
Following results are related to the third topic - differences in switching behaviour.
2 Effects on IGBT switching behaviour
The individual switching behaviour of the IGBT and the free wheeling diode in a parallel operation is determined by semiconductor parameters and circuit impedances of individual chips or devices. Our investigations related to the variation of semiconductor parameter have shown that the most sensitive value is the Transfer Characteristic, which can be described as a function of the Threshold Voltage VGE(th) and the Transconductance gfs. Differences in both values have a similar effect on the current distribution during switching of parallel IGBT. In both cases will the current difference in the Transfer Characteristic at the Gate Emitter voltage plateau VGE(pl) cause a difference in current during switching (see also Fig. 2). A variation of semiconductor capacitances has no strong influence on the switching behaviour. Only for the Miller-Capacitance (Crss) an effect could be observed. Constructive elements with influence on the switching behaviour are mainly parasitic inductances inside and outside the power semiconductor module.
2.1 Semiconductor parameter
2.1.1 Transfer characteristic
The threshold voltage for an IGBT can vary in a wide range theoretically, for example by 2V between 4,5V and 6,5V for SPT /3/ or 1,5V between 5V and 6,5V for TrenchStop-IGBT /4/. Switching one IGBT from the upper and one from the lower limit in a single chip application is no problem. The result would be different switching times and a different plateau level of the Gate-Emitter voltage, but the switching losses would remain the same.
Figure 2. Theoretical limits of the threshold voltage for IGBT chips with nominal current of 100A and corresponding VGE(pl) level for a total current of 200A in a parallel connection of such devices
The same two IGBT in a parallel connection switched with one gate source would have the same Gate plateau level VGE(pl) (also called Miller – plateau) and according to the Transfer characteristic (Fig. 2) extremely different currents during switching. Different switching losses are the consequence. Because no samples from the limits are available the investigation can only be done by circuit simulation. Figure 3 shows a turn-on and turn-off with a difference in VGE(th) of 1V assuming that both devices have the same Transconductance.
Figure 3. IGBT collector current of two parallel chips during turn-on (upper) and turn-off (lower) in a circuit simulation with different VGE(th) +-0,5V
The IGBT are switched at the nominal current of 100A. The device with the lower Threshold voltage switches on first, taking the bigger part from the total output current, producing more switching losses of about 15%. At turn-off the device with the lower Threshold switches later and taking therefore again an increasing part from the total output current. It has therefore also higher turn-off losses of about 30% compared to an even distribution.
Fig. 4 shows the difference in switching losses for the whole possible range of a threshold voltage spread from 4,5V to 6,5V. An IGBT from lower specification limit LSL would have 3 times the switching losses compared to a device from the upper specification limit USL. For typical inverter applications with a similar value of switching and conducting losses an output current reduction of about 20% would be necessary to keep the junction temperature at the level of two identical devices.
Figure 4. Relative difference of total sswitching energy (turnon + turn-off) between two parallel IGBT chips as a function of dVGE(th)
An operation with more than 2 chips would become very critical because an increasing current de-rating would be necessary. For a practical relevant approach the statistical possibility of such a set of devices should be considered. In practice is the possibility to find two devices from the opposite limits nearly zero. A typical distribution of a lot of 800 chips is given in Fig. 5 and Fig. 6. Similar figures can be found for the whole production of several 100.000 chips in 2005. A small shift of the expectancy value x of less than 100mV has to be taken into account for statistical consideration.
Figure 5. Probability of VGE(th) measured during the production test of IGBT modules (100A, 1200V SPTIGBT, VGE(th) at 4mA)
The variance for the shown distribution is 43mV and the maximum difference between two individuals is here 300mV. The probability to find 2 chips with ΔVGE(th) = 400mV is lower than 1ppm for the whole year production. Taking this probability as a practical acceptable value for a reliable series production the difference of switching losses in parallel operation is reduced significant.
Figure 6. Typical distribution of IGBT threshold voltage from production test
For a higher number of “n” parallel chips is the worst case that 1 IGBT with low VGE(th) and n-1 IGBT with a high VGE(th) are connected in parallel. If the probability of 1ppm is kept constant to find this combination, than the difference in VGE(th) decreases. This is due to the fact that the probability to find “n” chips from the specified limits decreases rapidly with the increasing number of n. According to the existing parameter distribution the limits for different VGE(th) with a probability of 1ppm can be specified for a multi chip application:
• ΔVGE(th) (2 chips) = 400mV
• ΔVGE(th) (4 chips) = 300mV
• ΔVGE(th) (6 chips) = 200mV
The simulation with this new limits shows, that the maximum of switching losses in one device will be reached for 2 to 3 chips with 10% more than typical specified (Figure 7)
Figure 7. Difference of Switching Energy for an increasing number of parallel IGBT, ΔVGE(pl) chosen for a probability of 1ppm
A measurement with 2 devices and a difference of VGE(pl) of 200mV is shown in Fig. 8. Each device has its own Gate resistor of 4,3Ω and Emitter resistor of 0,5Ω to stabilize the parallel operation during switching. The device with the lower VGE(pl) has approximately 10% higher Eon which corresponds well to the simulation results from above.
Figure 8. Measured turn on of two parallel 400A IGBT with dVGE(th) = 200mV; E(on)1 =33mJ; E(on)2 = 36,8mJ (RG(on) = 4,3Ω RE =0,5Ω per module; VCC=600V; Tj=125°C; IC=300A)
It does not exist a database about the variation for these parameters neither in the data sheet nor from production tests. This would be necessary for a worst case analysis. Measurements of the input capacitance Cies for a selection of 400A IGBT modules show a variation of only +/-5% (see Figure 9).
Figure 9. Measured Variation of semiconductor capacitances of 400A IGBT modules (1MHz; 100mV; VCE = 25V; 25°C)
Nearly no influence of Collector-Emitter capacitance CCE and Gate-Emitter capacitance CGE (= Cies-Crss) on Esw could be observed in a parallel connection. To prove this statement CGE of one module was increased by an additional capacitor (CGE(ext) = 4,7nF = approx. 20% of average value) directly between Gate end Auxiliary Emitter. Even in this case the Collector voltage and the Collector current of both devices are nearly identically.
Figure 10. Turn-on of 4 parallel IGBT modules Module 1 with additional 4,7nF capacitor between Gate and Emitter; (RG(on) = 4,3Ω RE =0,5Ω per module; Tj=125°C; IC [100A/div]; VGE [5V/div]; VCE [100V/div])
Only the Miller capacitance CCG = Crss has an influence on the switching losses. The IGBT with the higher value shows a increase of Eon, but this is partly compensated by a decrease of Eoff .
2.2 Mechanical construction
In result of the mechanical construction mainly parasitic inductances are the cause of different switching behaviour. At the chip level the inductance between IGBT and Auxiliary Emitter inside of a module has a direct influence on the switching behaviour because of its positive feedback into the Gate circuit. Different inductances between parallel chips will lead to different switching speed. Beside of the risk of oscillations and a loop current induced by a high di/dt the effect on the total switching losses in hard switching applications is small. This is because higher turn-on losses by a lower inductance compared to the parallel IGBT will be compensated by smaller turn-off losses. Where the inductances inside of a module are often topics of publications /5/ /6/ is the external inductance in large inverter applications much more crucial. Caused by large dimensions and mechanical restrictions inside of a switchboard asymmetric current loops for the parallel semiconductors are the consequence. Figure 11 describes an inverter design with 6 modules per phase in parallel. All modules are in one line beside each other. A similar test assembly (see Fig. 12) was used to investigate the relation between device variation and the influence of an unsymmetrical construction.
Figure 11. Inverter Design with 6 Modules (yellow) per phase in parallel. DC and AC terminals are on the left hand side of the switchboard
Figure 12. Test Assembly for one Inverter phase leg
The test devices are special selected, where the device with the lowest VGE(pl) is at position 1 and the one with the highest VGE(pl) is at position 6. Devices 2 to 5 are average devices (see for example Fig. 14). The first measurements were done with the AC and DC terminal in a symmetric middle position. These present the influence of the parameter variation. The peak current during turn-on from an inductive load is about 760A +/- 85A which corresponds to a difference of about 11%.
Figure 13. Peak current during turn-on with symmetrical AC terminal position between device 3 and 4 (200A/div)
Figure 14. Relation of peak current to plateau voltage for 6 parallel devices in a symmetrical configuration
For the second measurement series the AC terminal was moved to a position between device 1 and 2. Now the difference in peak currents is about 450A compared to 170A with symmetric position (see Figure 16).
Figure 15. Peak current during turn-on with asymmetrical AC terminal between device 1 and 2 (200A/div)
Figure 16. Relation of peak current to plateau voltage for 6 parallel devices in an asymmetrical configuration
The highest peak value is 35% higher than the average value. From the previous test we know that 11% come from the device parameter variation and now additional 24% from the asymmetric AC terminal position.
Figure 17. Short circuit current with external short circuit loop (L about 2μH), turn-off by Vce(sat) monitoring (500A/div)
Figure 18. Peak current at short circuit trun-off with the AC terminal in middle position
The last measurement is a “soft” short circuit, also called type 2 with a short circuit impedance of some μH. In that case only the AC-terminal position dominates the current distribution for any layout and device parameter set. All tests with the different layouts show that a equal circuit impedance from the power source (here DC-Link capacitor) to the device and from there to the load is essential for a symmetric current distribution between parallel modules. It is often not possible to avoid this unbalance totally but it can be reduced by a direct 1:1 relation of DC-Link capacitor to the IGBT and by an AC terminal construction whit similar length between the parallel IGBT-modules and the point where the load cable is connected.
The devices from the upper and lower measured limit of parameter distribution can differ +/- 10% in the switching losses and asymmetric current sharing during switching. An operation of n-chips or modules in parallel with practical relevant parameter distribution is possible without preselection in a well designed symmetrical construction. The remaining differences are well within the design margin, when designing with a junction temperature 25K below the maximum junction temperature. An unsymmetrical construction can add a much higher percentage to the switching losses compared to the parameter variation.
/1/ U. Scheuermann; “Paralleling of Chips – From the Classical ‘Worst Case’ Consideration to a Statistical Approach”; PCIM Nürnberg; 2005
/2/ interactive Power Electronic Seminar; ETH Zürich; http://www.ipes.ethz.ch/
/3/ Data sheet and product information for SPT IGBT http://www.abb.com/
/4/ Data sheet and product information for TrenchStop IGBT http://www.infineon.com/
/5/ O. Usui; H. Nakatake; T. Oho; “Analysis of the Dynamic Characteristics of a Power Semiconductor Module, Considering the Influence of Electromagnetic Coupling Between Wiring”; EPE Dresden; 2005
/6/ S. Bontemps; “High Frequency and Paralleleing Modules for High Current”; Power System design Europe; 12/2004
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