Posted on 30 August 2019

Low Inductive Inverter Design

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Using a new power module concept

Increasing efficiency and lowering EMI are important goals for designing power electronic systems. To obtain this, the parasitic inductance of the current commutation loops is under focus. In this paper an overall low inductance module is shown which provides not only low inductance within the half bridge but also low inductance among half bridges itself, e.g. in a three phase inverter. The new module concept enables not only optimized 3 phase systems but also optimum performance of three level NPC (Neutral Point Clamped) inverters.

By Xi Zhang, Daniel Domes, Reinhold Bayerer and Alexander Herbrandt, Infineon Technologies AG


In power electronic systems fast transient in voltage and current is the consequence of the basic functionality. High di/dt value at current commutation in conjunction with parasitic inductance induces voltage Vind across the parasitic inductance Lσ:

Equation 1

 Another disadvantage coming along with Lσ is the low resonance frequency of the resonant circuit formed by the parasitic chip capacitance Cchip and the stray inductance Lσ:

Equation 2

In Figure 1 a 1200V/400A low inductance half bridge module shows of having only 5nH internal stray inductance, first presented in [1]. Such low inductance value is realized by strictly ensuring strip line design and current flows only in one vector plane. The consequences is dramatically reduced over voltage peak and no ringing.

Low inductance half bridge module enabling lowest parasitic inductance by having line-wise DC-connectors

Three phase topology

The low inductance half bridge module from [1] seems to be an ideal candidate for realizing a 3-phase inverter system. The superior switching behavior is the result of not only optimizing the module but also the bus bar and the capacitor. Such an optimized half bridge system is shown in Figure 2 left, schematically. As demonstrated in Figure 2 right, the parallel arrangement of three of the half bridge systems leads to a three phase inverter. Often the interconnection between half bridges is not optimized for low parasitic inductance. The target of the work in this paper is to eliminate the inter-half-bridge inductance, as well. This requires an overall strip line design for the whole inverter (3 half bridges) including DC-capacitor.

Inductance-optimized half bridge system (left) and conventional arrangement of these half bridge systems

Low inductance connection between half bridges is relevant for commutation among half bridges. This happens when the so called zero-state is set by means of the control system of the inverter, for example. Zero-state means that all top and bottom switches are turned on, respectively. Then, a freewheeling loop appears and the load current is running free through transistors and diodes of either the top or bottom side. No current goes into DC capacitors anymore and all load branches are connected to the same potential (DC+ or DC-). After this zero state, the modulator continues with non-zero switching states and currents commutate from freewheeling paths into capacitors.

In Figure 3 an example for inter-half-bridge commutation is shown in a simplified way. Assuming that the DC-connection to the mains is not applied for the moment of commutation, in the left picture a zero state is shown, whereas all top IGBTs are turned on. Assuming further that the load current in the middle and right half bridge is flowing into the phase connection, the top diodes of the mentioned half bridges are conducting. The sum of these currents is flowing out of the phase terminal of the left half bridge, whereas its upper IGBT is conducting. If the modulator continues with a non-zero state, the upper IGBT of the left half bridge can be turned off, for instance. Figure 3 right shows the situation directly after the IGBT turn-off. The stray inductance forces current flow although the IGBT is already turned off. In this example the consequence is that the energy stored in the stray inductance goes into the DC cap of the left half bridge. This effect is causing an overall higher RMS current of the DC caps compared to low stray inductance design.

Simplified example for inter-half-bridge commutation in a 3-phase inverter with stray inductance in the half bridge to half bridge connection


Three level NPC inverters are usually built out of standard modules. Depending on the power factor of load different commutation loops exist where two (short commutation) and even three (long commutation) half bridge modules are involved [2]. Therefore the low inductive connection from half bridge to half bridge is quite of interest, especially in 3 level application.

Proposed Solution

Low inductance commutation loops between half bridge systems can be arranged by strictly following the principles mentioned in [1]. These are listed next.

Consequent realization of strip line conductors without interruptions in geometry

Arranging the commutation current flow always in y-z-plane (see example in Figure 1).

The outcome of that is a module concept as shown in Figure 4. This approach combines three half bridges, within each half bridge the chips are paralleled along the x-axis. Three half bridges are arranged behind each other along the y-axis. To achieve lowest inductance throughout the whole arrangement of 3 half bridges a multilayer DCB is used. It allows a DC- layer over the whole length of the module, along the y-axis. The individual half bridges are carried by a second layer of DCB, which connects down to the first layer at each DCside. DC+ and Phase (Ph1 to Ph3) are brought up by means of a line wise connector for each individual half bridge. Strip lines in the multilayer DCB and above the chip layer result in an overall low inductance inverter.

Three-phase concept module for lowest overall inductance


For three phase systems and three level NPC topology the low inductive connection of individual half bridge circuit is important. A new module concept is demonstrated which combines properties, reducing the stray inductance while fulfilling the need of current flowing in the y-z-plane of Figure 4. Following this design leads to an overall reduced inductance, excellent current sharing and lowered RMS current at the DC capacitors.



1) Reinhold Bayerer, and Daniel Domes, "Power Circuit design for clean switching," CIPS 2010, Nuremberg, Germany.
2) Zhang Xi, Uwe Jansen, and Holger Rüthing, "IGBT power modules utilizing new 650V IGBT3 and Emitter Controlled Diode3 chips for three level converter," PCIM, Nuremberg, 2009, Germany.



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