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Posted on 01 April 2019

Main Switch Active Clamp Forward Converter Transition Examined

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Understanding the sequence of transitions lead to better design

The active clamp topology is one of the more popular topologies in that it allows for efficient conversion of a buss voltage to a voltage needed at the logic ICs in an electronic subsystem.

By John Bottrill, Texas Instruments

 

A review article of the active clamp topology turn off reset switch already has been published [1]. This article completes the switching cycle description. It describes the main switch transition from “ON” to “OFF” and the voltages and currents in the circuit to the point where the “active clamp” switch is turned on. This narrative of the active clamp switcher is for when there is continuous current in the active clamp forward converter’s output inductor. The transformer presented is a theoretical model that represents the leakage inductance, LL, the magnetizing inductance, Lm, and the coupled windings, Np and Ns, as separate elements.

The description starts at mid-point of the cycle’s power portion and uses the circuit shown in Figure 1 as the basis for discussion. Positive currents are indicated by the arrows. The switches Q1 (active clamp switch) and Q2 are shown with their inherent body diode and drain-to-source capacitance. The Q3 and Q4 gate-to-drain capacitances are also shown because they affect the currents.

Topology, voltages and currents

To simplify the oscilloscope waveforms, the primary and secondary ground references are connected together to make a common ground.

The initial conditions are: Q2 is on and the current through Q2 (Iq2) is equal to the current from Vin (IIN). Q3 is turned on and is carrying the current through the secondary winding Iout. Both Q1 and Q4 are off. The drain of Q1 has a voltage of approximately negative 2 Vin biasing it and the drain of Q4 has a voltage of Vin*(Ns/Np). The current Iin flows through the primary winding of the transformer, pins 1 and 2, flowing first through the leakage inductor LL, and then is split into Im and Ip. Im is the magnetizing current that flows through Lm and Ip is the current coupled to the secondary through the primary winding Np.

Im and Ip currents then rejoin and flow from the transformer at pin 2 and through the switch Q2.

The current Ip through Np is reflected by a current Is equal to Ip*(Np/Ns) that flows out of the secondary of the transformer at pin 4. The result is flux cancellation in the core for these two currents.

On the other hand, the magnetizing current is the result of the input voltage across the primary side magnetizing inductance. This current is increasing at a rate of Vin/Lm.

The secondary side voltage of the transformer at pin 4 is greater than the output voltage. The difference results in an increasing current through the output inductor during the time that Q2 is on. This current is also increasing at a rate of ((Vin*(Ns/Np)) – Vout)/Lout. This changing current, when reflected to the primary side, has a higher rate of change than Im. Because of this, it is usually the only current slope considered when calculating the control loop.

The transformer in the unit under test has a turn ratio of 6-to-1, so you will have to take that into consideration when viewing the waveforms.

Because of the voltage across the transformer’s pins 3 and 4, Q3 is biased on and the gate side of the Miller capacitance of Q3, and Cgdq3 is biased high. As the transitions start Q1 is off, and there is a negative voltage on the drain of this P-channel FET. Assuming 50 percent duty cycle the voltage across Cr is approximately twice Vin and the voltage on the drain of Q1, a P-Channel FET, is 2*Vin below ground.

Because Lout and Lm are relatively large compared to LL and we are talking about a time frame of approximately 120 nanoseconds for this event, we will assume that Iout (the current through Lout) and Im (the current through the magnetizing inductor) remain constant throughout this discussion.

The sequence of events about to be described has five different stages. The beginning and end of each stage is marked on the scope shots in Figures 2 – 3 at t1, t2, t3, t4, and t5 respectively.

Voltages on the transformer pins 2 and 4.

Voltages on the Transformer Pins 2 and 3

Starting at time t1, the control circuit turns off Q2. This is a very fast transition. Because of the significant drain to source capacitance of Q2 and Q1, this is a zero voltage transition from low to high impedance of Q2.

The current out of the transformer’s pin 2 is now charging the inherent drain to source capacitances of Q2 and through the reset capacitor Cr to Q1, resulting in a linear increase in voltage on the transformer’s pin 2 and a corresponding increase in voltage on the drain of Q1.

We now need to look at the relative voltages.

The voltage increase on pin 2, voltage at time t1, is reflected across the transformer winding. This results in a decrease in voltage on pin 4. Because the voltage across the Np and Ns windings must remain balanced, there is a change in voltage on the drain to source capacitance of Q4, and the gate to drain capacitances of Q3 and Q4.

The current in Lout is not going to materially change, so the current coming out of these three capacitances has to be a result of changes in Is and hence Ip. This slight change in current in Ip results in a balanced rates of change in voltage across the primary and secondary capacitances.

Up to this point, while Q3 is turning off, the output inductor can pull all the current it needs through the FET itself (the gate resistor delays the turn off of the FET). The body diode of Q4 is reversed biased.

During this portion of the transition the voltage on pin 2 is still below Vin. So the primary current, Iin into the transformer, has no reason to decrease. The voltage across the output inductor has changed as the voltage on pin 4 decreases to reflect the decreasing voltage across the primary winding. Since pin 4 of the transformer is decreasing, the voltage across the output inductor changes. Now the output voltage Vout exceeds the voltage on pin 4 of the transformer.

These factors continue to change at a constant rate as the current Iin continues to linearly charge the drain to source capacitances of Q1 and Q2 until time t2 when the voltage on pin 2 reaches Vin (50V), the voltage on the drain of Q1 reaches –50V, and the voltage on pin 4 reaches zero volts.

During the time, t2 to t3, the current through the primary leakage inductance is still almost the same as at the start of the transition and the voltage on pin 4 continues to decrease. This is reflected in the voltage on pin 2 exceeding the voltage on pin 1 of the transformer.

Any change in the input current is due to charging and discharging the gate to source capacitances of the output switches and will be slight.

Reversing voltage across the primary causes the voltage on pin 4 to continue decreasing, going below ground, while pin 3 remains at ground as Q3 continues to turn off. See Figure 3.

The voltage across the FET Q4 has not decreased enough to pull current through the body diode of Q4. At the same time Q3 has not completely turned off. This forces the output inductor to continue to draw current from the transformer’s secondary. The result is continued current in the primary and increased voltage on pin 2. This will continue until time t3 where the body diode of Q4 starts to conduct. Now the output inductor current can be drawn from both pin 4 of the transformer and through Q4. The primary side leakage inductance now is developing a voltage to balance the increasing voltage on pin 2 so that current can continue to be drawn. This starts to decrease the input current Iin reflecting the decrease in current through Q3 as the Iout current starts to transition to the body diode of Q4.

Time t3 to t4 reflects the transition of the output current Iout from being drawn from the Ns winding to being drawn through the body diode of Q4. This decrease in current in the Np and Ns winding, which is represented by the slope of the Pin 2 voltage of the transformer decreasing, flattening out as the current through the transformer primary Np decreases.

At the same time the voltage on pin 3 is increasing, as is the voltage on pin 4, which was negative. The result is a near zero differential change across pins 3 and 4 of the transformer, but a positive voltage shift of the entire winding. This is turning off Q3 and turning on Q4. The currents necessary to do this charge the gate to drain capacitance of Q4, discharge the gate to drain capacitance of Q3, enter pin 4 and leave pin 3. This current is provided by the primary side magnetizing current, which is at a peak at this point in the cycle.

The magnetizing current Im flowing through Np flows in the reverse direction of Ip. This causes the Is current to reverse so that the gate of Q4 can be charged. Because the magnetizing current, Im, is now effectively going through Np, it now draws current from Vin and sends it to charge the drain-to-source capacitances of Q1 and Q2. Thus, significantly less (or no) current is coming out of pin 2 to change to the voltage on pin 2 of the transformer. The result is a relatively flat voltage on pin 2 between t3 and t4 already mentioned.

At this point, the cycle is almost complete. Q4 is conducting through the internal diode and is starting to be turned on, but will be turned on harder during the t4 to t5 segment.

For the time between t4 and t5, the magnetizing current is split between charging the drain-to-source capacitances of Q1 and Q2 and discharging gate-to-drain capacitance of Q3, and charging the gate-to-drain capacitance of Q4 even further. Since these capacitances are not linear and the voltage across Q3 is increasing, the amount of current needed will not be a constant. This current, Im, is provided from Lm, so the voltage on pin 2 will reflect the non-linearity of the transition.

At t5 the drain-to-source voltage of Q1 has climbed from –2 Vin to a diode drop above ground and the internal body diode starts to conduct. This means that any further current out of pin 2 now starts to change the voltage across Cr, which is a much larger capacitor. So the change will be extremely slow and insignificant compared to what has been happening.

At this point the transistor Q1 can be turned on in a lossless manner. This completes the lossless primary side switching. The secondary side transitions are also relatively lossless, as the switch of the current from one rectifier to the other is done at zero volts through the internal parasitic body diodes.

Conclusion

In summary, an understanding of the sequence of transitions within this portion of the cycle can lead to better designs. We have identified the role that each of the elements of the transformer and output switches play when turning off the main switch by transitioning the output switches to turning on the clamp switch.

 

References:

[1] Bottrill, John, “A discussion of the Active Clamp Topology,” Bodo’s Power Systems, Pages 46-48, September 2007:
http://www.bodospower.com/pe/restricted/downloads/bp_2007_09.pdf
.
For more information about power solutions from Texas Instruments, visit:
http://focus.ti.com/docs/prod/folders/print/ucc2897a.html
http://focus.ti.com/docs/prod/folders/print/ucc2891.html

 

 

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