Posted on 06 November 2019

Miniaturisation of High Voltage, High Capacitance Multilayer Ceramic Capacitors

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There is a constant battle to reduce size and weight of electronic components. Moore’s law supposes that for computing hardware the number of transistors on an integrated circuit doubles every 2 years. Assuming that available space for these components does not increase - in fact it is generally desirable that this space decreases - it follows that the component size must dramatically reduce to compensate.

By Matt Ellis, Senior Application Engineer of Syfer Technology

The techniques and practicalities of handling and mounting discrete components, as distinct from those for semiconductor wafer processing, means that there is a baseline to size reduction which is rapidly approaching. There have, however, been constant improvements in manufacturing and materials technology over the past few decades allowing for miniaturisation of Multilayer Ceramic Chip Capacitors (MLCCs). Significant they may have been, but none the less not quite to the extent found in semiconductor manufacture. Volume manufacturers have pioneered these developments with the current commercially available pinnacle being the sand grain like 01005 EIA case size - surface mount capacitor only 16 thousandths of an inch by 8 thousandths. One such manufacturer has claimed a further improvement with a metric 0201 size, 0.2mm x 0.1mm or 0.008” x 0.004”.

The focus of this miniaturisation has broadly been in the field of base (or noble) metal electrode technology. Improvements in tape casting and other processes have facilitated these improvements but they generally only apply to low voltage components, a quick search of the main manufacturer’s ranges reveals that the typical maximum available voltage, even in the now commonplace 0402 case size, is only 100Vdc with some suppliers pushing up as high as 250V in class 1 dielectrics. For higher voltage, large capacitance value and high power applications there is still a need for larger size components although miniaturisation can still provide significant benefits.

The space and aerospace industries are the primary beneficiaries of component weight reduction; according to NASA it costs $10,000 to put a pound of weight (454g) into space, that’s $22 a gram so any drop in weight can lead to significant savings. The drive towards greener technology means that weight saving in any transportation system is also of benefit. With the increase in development and production of electric and hybrid electric vehicles the use of high voltage, and high voltage high capacitance, MLCCs is on the rise. Despite this demand miniaturisation has not occurred at anything like the pace of smaller low voltage components and it could be argued that, especially in the field of SMPS leaded capacitors, that technology has remained static. There are reasons for this; designers can be tied to MIL specifications which dictate a certain part, or range of parts, but there are also technical issues to overcome as well.

Graph showing strain vs DC bias for X7R MLC Capacitor

The limits of capacitor design are defined by their failure modes and there are many failure modes which limit the extent to which mid to high voltage MLCCs can be developed. There are extrinsic failure modes, such as mechanical and thermal cracking, but we will look at the intrinsic ones which are in the hands of the manufacturer. The limiting factor for MLCCs has changed over time, early types were limited mainly by the quality and purity of the dielectric materials themselves with point defects and contamination limiting the maximum number of layers and the minimum thickness of those layers. Generally speaking the higher the capacitance the lower the reliability as there is a greater total area of electrode overlap and therefore the likelihood of a point defect. As dielectric materials, together with materials preparation and processing, improved the limiting factor became the dielectric strength of the material itself. Once this problem had been overcome one could imagine that thicker and larger parts could be manufactured without fear of dielectric breakdown or point failures. Not to be as a new failure mode appeared - electro-mechanical stress cracking. Commonly referred to as piezoelectric effect it can also follow electro-strictive behaviour (figure 1) and has been the failure mode to limit MLCC advancement for some time now. It affects most class II barium titanate based dielectrics and becomes an issue for case sizes 1210 and upwards, with voltages above 200V. The crack typically runs through the centre of the component along one or two dielectric layers (figure 2).

Typical “Piezo” crack failure through centre of MLC Capacitor

In order to increase the available capacitance for a given footprint, the common solution is to ‘stack’ capacitors together with lead frames. However, it is not only labour intensive, and therefore costly, but can also lead to different reliability issues. Other solutions could involve special dielectric formulations, but these are usually a trade-off for the dielectric constant and will affect the ultimate capacitance value available.

The Syfer Technology solution to the limitations imposed by electromechanical failure is to invent StackiCap™ - a single chip design to provide high CV in compact packages and offer the greatest volumetric efficiency and CV per unit mass of any high voltage X7R ceramic capacitor available. After a series of trials and iterations this novel product and unique manufacturing process has a ground-breaking patent pending - GB Pat. App. 1210261.2.

Exploiting the manufacturing and process benefits of being a single unit, whilst allowing the capacitor to exhibit the electrical and physical behaviour of multiple, thinner, components, StackiCap™ employs an inbuilt stress relieving layer. This layer is made up of a combination of already utilised material systems and is formed during the standard manufacturing process. The layer is positioned in the place/s where mechanical stress is the greatest allowing for mechanical decoupling of the multiple component layers. At this time 2, 3 and 4 “stack” versions have been trialled (figures 3, 4 and 5).

stress relieving layer under Optical magnification, SEM Magnification and at macro level pre-termination

StackiCap™2220 vs 3640 2 stack MLC; StackiCap™2220 vs 8060 MLC

As no lead frames are required, standard tape and reel packaging, with pick and place capability, is available. In addition Syfers’ Flexi- Cap™ polymer flexible termination is included as standard. The potential benefits are significant. For example the space and weight saving for a 1kV 330nF stacked leaded component against the equivalent in StackiCap™ technology (2220 1kV) would be 0.56cc volume down to 0.12cc, a factor of 4.5 with weight of 3.2g down to 0.63g, a reduction factor of 5. In NASA terms this example this would give a $56 saving per component just in payload costs – and this type of component is often used a number of times in each application so the size, weight and resultant cost savings can mount up quite significantly.

StackiCap™ technology can also reduce board area significantly, even when replacing existing non-stacked alternatives. Often designers are restricted in the X-Y planes but not Z, so in extreme cases an 8060 size can be replaced with a single StackiCap™ 2220 (figures 6 and 7).

StackiCap™ capacitors are suitable for a wide range of applications such as switch mode power supplies for filtering, tank and snubber; DC-DC converter; DC block; voltage multipliers etc. and will provide huge benefits in applications where size and weight is critical. The range currently comprises case sizes 1812, 2220 and 3640 for commercially availability with case sizes 5550 and 8060 under development. This range is fully compliant with the RoHS Directive.


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