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Posted on 17 July 2019

Mixed Signal and Power Integration Packaging Solutions

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Multiple-die packaging techniques for very mixed silicon processing requirements

Even before the first transistor was invented, there has been a constant drive to integrate more and more functionality into a single product. There are the obvious cost benefits to put more functions into the same package or die area, but there are also performance benefits by integrating more devices into a single product.

By Jim Gillberg, Fairchild Semiconductor

 

For high speed functions every signal that must be connected from one integrated circuit to another slows the system down by the addition of significant input/output capacitances for each pin and PC board routing which requires larger line drivers with more cost and more board area.

In the realm of integrated circuits, this constant need for higher integration has for the most part been achieved through constant improvements in the photolithography used to fabricate the devices. Equipment has evolved from contact printing with .1 mil resolution through projection printing, high resolution steppers to direct write on wafers with E-beam technology where we now talk about nanometers of photo resolution. For awhile this progress has followed what has gotten to be known as Moores’ law. This defines the ever-increasing complexity of a product that can be integrated onto a piece of silicon. This has defined the progress over time for microprocessors, silicon memory, and ASICs. While process complexity has increased to be able to define these extremely small feature sizes, today’s basic lateral CMOS transistors would be recognized by its original inventor. This drive for continual improvements and integration has been around even before semiconductors where the primary driver. Figure 1 is a diagram that highlights this constant evolution in technology pushing for ever more complex systems.

Kurzweil’s extension of Moore’s law

There has been a similar drive for smaller, less costly and higher performance power devices. However advancements in the RDS(ON) (on resistance) of the power devices while taking advantage of improved photolithography has been enabled by new and more complex structures. The current power MOS devices developed do not use the traditional planar topologies that had been used for many years, but they have been replaced with much more complex trench or charge-balanced technologies. Both of these approaches add process complexity to significantly lower the specific on resistance of a given MOSFET as compared to the older planar technologies.

Example of Planar vertical DMOS, Vertical Trench and Charge Balanced Power MOSFETs

These new power structures have driven an improvement curve for the specific on resistance per unit area of a MOSFET. Figure 3 shows a generic curve for the on resistance of a typical 50v MOSFET process and is similar in shape to Moores’ Law but for Power devices.

RDS(ON) Vs time

As system complexity grows, it becomes natural to want to combine both higher performance mixed signal IC functions with higher power silicon switches. However, when you look at the process complexity required for combining high performance mixed signal control with significant power handling capability it quickly becomes obvious there has to be a better way than to just integrate everything into a bigger more complex single piece of silicon. In addition to the process complexity one major drawback is for the high performance vertical DMOS or other power structures the back side of the die is the drain (or collector) of the power device with current flowing vertically through the die. In contrast most mixed signal ICs have a P-sub- strate material where the back of the wafer can serve as a system ground. Having the back side of the die being the output from the power device can cause other issues related to handling over or under voltage transient conditions that might cause unexpected results.

Because of the issues in trying to integrate the process complexities of the advanced power structures with high performance mixed signal designs the use of advanced packaging techniques normally will produce the best results.

Following is an example of a complex high power automotive solenoid driver. Two different approaches were taken. One combining the high power switch with the high performance control block into one piece of silicon and the 2nd an example how using advanced package and isolation techniques can reduce the cost of a product. A series of generic assumptions are made on the silicon cost of each product to obtain a comparison of the two approaches:

Assumptions: (Following is used for illustrative purposes and are generic costs and mask counts)

Vertical DMOS 6 inch wafer 9 masking levels @ $30/level

High Voltage BCD DLM process – 24 masking layers $30/ level

Using a normalized area of the integrated solution on the left to be 1unit area: then the power fet and control die (on the right side) each have an area of about .3 units as compared to the larger monolithic solution. Thus the total silicon area is 40% lower using the two die vs. the integrated solution.

To obtain a reasonable cost comparison you now have to take into account both the area difference and masking complexity of the three devices. Using the assumptions above for wafer costs would generate about a $1.00 cost for the integrated solution while generating a combined $0.40 cost for the two die solution. Thus by selecting an architecture dividing the power from the control in this example generates a 60% cost reduction in the silicon. While there would be some cost increase in the assembly of the additional die in the package the combination of silicon and packaging costs for this example will be much lower for the divided solution.

For this example to hold true the power section of the device must be a major portion of the overall die. Again in this example the power portion of the integrated solution is approximately 50% of the total silicon area. Thus a major cost reduction through partitioning should be expected. In addition, the area of the silicon required for the power region has to be large enough that the silicon cost reduction can overcome the increased cost of the assembly. So for higher impedance power devices, above about 100 milliohms of rdson, a monolithic solution normally will have the lowest cost. While for power systems requiring MOSFETs with less then 50 mOhms of on resistance, a partitioned architecture will normally be lower cost. However this tradeoff has to be continually evaluated as new technologies can change the cost and area assumptions used above.

One of the major issues that must be over come when combining power and control in a single package, is that the back of the power device is normally the drain or collector of the power switch, so the control die must be electrically isolated from the die attach area that the power die is mounted on. Since the power die is typically a vertical conducting device, a good low resistance high temperature solder die attach is normally used. There are several ways to approach the electrical isolation required between the power and control devices.

Separate the die attach areas:
Use of non conducting epoxy for the control die.
Use of polyimide tape die attach for the control die.
Use of a back side laminate on the control die.

In the example shown two types of isolation are used. To start there are three separate die attach areas in the package show above in figure 4 on the right. ( left, right and center) Each of these die attach areas or paddles can have a different electrical potential. On the left and right die attach areas the power device is soldered to the paddle while the control IC uses a backside polyimide laminate that electrically isolates the die from the paddle that the power device is attached to.

Alternate Approaches to Smart Power Products

Each technique for isolation has its advantages and disadvantages as regards, cost reliability and manufacturability.

Some packages like the MLP or PQFN devices (similar to the package shown in figure 4) can easily accommodate multiple die attach areas. But traditional power packaging such as the TO220 or TO252 which have a thick header or tab are not easily divided into two separated electrical areas. Use of a non-conducting epoxy die attach is one of the easiest isolation solutions to implement but this approach has been shown to be susceptible to reliability issues related to pin holes in the epoxy die attach.

Polyimide tape is being used successfully but the die attach area must be larger then the attached die area to account for the alignment tolerance of the die to the polyimide tape and thus takes up more area then the backside laminate solution mentioned. For the back side laminate solution a film is attached to the entire backside of the control die wafer and then the die are sawn from the wafer. In this way each die has the polyimide film attached to the back of the die and the need for additional area to account for the alignment variability when attaching the die is eliminated. This can be particularly beneficial when the control die is being attached on top of the power die, allowing a smaller power die to still accommodate the die on die assembly requirements. Figure 5 shows the back side laminate and a wafer with the laminate attached.

Backside laminate isolation

So as we continue to follow the inevitable path of higher level integration and more “systems on a chip”, and we begin to mix high power capabilities into these systems, you will find more often than not the product you are evaluating actually has several silicon die molded into it. So advanced multiple-die packaging techniques continue to be used to solve the problem of how to integrate products with very mixed silicon processing requirements while minimizing product costs.

Various multiple die assemblies

 

 

 

 

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