Posted on 08 May 2019

New Packaging Technology enabling High Density Low Inductance Power Modules

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While chip technology (IGBT, SiC MOSFET) is evolving step by step allowing for higher current densities, faster switching and higher junction temperatures, the applications become more and more limited by the power module packaging technology itself. By using a multilayer flex foil applied in a sintering process vs. traditional bond wires, current design boundaries are pushed far out.

By Oliver Tamm, Head of R&D Sintered Modules, Semikron

Power systems engineers face always the same issues. While new chip generations allow for higher switching currents, higher operating chip junction temperatures and higher power densities, the final system performance is heavily dictated by the power module package. The stray inductance in the commutation path forces the engineers to lower the switching times to limit the overvoltage. Higher switching frequencies, which would allow for an overall much more dense inverter design, are not possible because of the associated high dynamic losses. Limited thermal durability of bond wires and solder joints makes it impossible to reach the operation temperature limits of new gen silicon without significantly reducing life time. But there is light on the horizon as power module packaging technology is undergoing significant enhancement to address these issues. Semikron has introduced the next gen 3D SKiN® technology allowing for higher densities and enabling new applications especially in the fast switching domain. By using a multilayer flex foil instead of bond wires and applying silver diffusion sintering to the whole stack consisting of heat sink, DBC, silicon and flex foil, density, reliability, stray inductance and thermal performance is pushed into new dimensions given system designers more freedom to squeeze more performance out of the silicon and footprint.

First Gen SKiN®

The first gen SKiN® technology has been introduced in 2011 [1]. Main motivation was to replace solder joints and bond wires by silver diffusion sinter joints to significantly improve reliability pushing power cycles up to 700k @ dT 110K and with that pushing silicon operation temperature closer to the chip limits without sacrificing module life time.

Figure 1 depicts a schematic cross section of such a module. Solder joints are replace by silver diffusion joints. Bond wire connections of the chip top side are replaced by a sintered flexible Cu foil. In fact the foil contact is based on an advanced 2 layer flex board.

Schematic cross section of the fi rst gen SKiN® module

While the lower layer of the flex carries the main high power current the upper layer takes care of low power auxiliary and sensor signals. Silver diffusion sinter joints have superior thermal stress durability as their solidus temperature is app. 960°C which is far away from the maximum operation temperature of the silicon devices. Furthermore while bond wires can only make contact to about 20% of the total metalized chip surface, the sintered flex foil exhibits a die contact area of up to 85%. The increased contact area and the thick metal layer improve the heat distribution, the surge current capability and in combination with the highly durable silver diffusion sinter joint it has greatly improved power cycling capability of such a device[2][3].

In the first SKiN® module generation ~650mm2 of silicon area could be placed on an DBC area of ~2400mm2 including all necessary control and terminal contact areas which counts up to a silicon to DBC utilization of ~ 28%.

First gen SKiN® module comprising of 4 x IGBTs and 2 x FWDs

As the thermal performance of the sintered stack (heat sink, DBC, chip, flex foil) is superior (~ 30% better vs. standard modules) it leaves significant headroom in various water cooled based applications to push for more silicon into the same footprint and with that significantly lower the overall costs. But how to place more silicon into the same footprint if the DBC is already fully populated with silicon, main power traces, terminal contact areas etc.?

Opening the next dimension: 3D SKiN®

The solution is straight forward but of course challenging: Move the DC-minus power trace resources from the DBC into a flex foil copper layer which is above the silicon chips. All real estate on the DBC which has been used for DC-minus power traces is now available for placing additional silicon. The 3D SKiN® was born.

Schematic cross section of the 3D SKiN® stack up

The upper layer of the flex foil (yellow color ) is used to form a module wide DC-minus power plane which can be connected to lower layers by the use of vias at any position of the module. The lower layer of the flex foil (purple color) bridges chip top sides to the appropriate DBC traces. The DBC itself has mainly only two conductor islands AC and DC-plus which furthermore makes the DBC design very simple and mechanically very robust. Moving from a pure single lateral layout towards a multilayer layout leads to a significant change in the module internal power routing. The chips are no longer arranged side by side from DC to AC terminal to form a half bridge configuration. The new architecture clusters the Bot switch to the AC island and the Top switch to the DC-plus island.

3D SKiN® module comprising of 6 x IGBTs and 6 x FWDs

The additional real estate on the DBC makes it possible to add ~50% of silicon (e.g. three instead of two IGBTs per switch). Due to the low Rth of the sintered stack the amount of added silicon nearly calculates into proportional increase of current, assuming that the water cooling flow is adopted accordingly to deal with the higher amount of power dissipation per module.

The density of the module is superior. Figure 4 depicts an example of a 650V half bridge module with 600A of nominal current. A similar design using 1700V IGBTs is rated @ 270A, all on a DBC area of ~2400mm2. The DC-minus plane (grey color) covers ~80% of the DBC area, allowing for an balanced current distribution over all silicon devices.

As free meals are usually seldom of course also the 3D SKiN® technology has its challenges. The electrical design needs much more considerations vs. traditional bond wire architectures or vs. the first gen SKiN® architecture. Controlling and guiding the electrical fields around the chips is more complex and the design needs to take care of appropriate cooling of the DC-minus flex layer. But the latter is also a strength. Due to its flatness, the flex foil can be designed in a way that it is tightly coupled with the DBC allowing for efficient cooling. Together with the high durable sinter joints, junction temperatures of up to 200°C become feasible and with that 3D SKiN® is very well prepared for the next chip generations.

1,5 MW three phase SKiiPX power module based on first gen SKiN modules

System benefits

Systems which are adopted to this new 3D SKiN® technology can be boosted up without changing the fundamental mechanical footprint. As an example, Semikron's SKiiP® X system [4] which is based on the first gen SKIN® technology and which already marks a huge step in the industry in respect to density and modularity, may see a further power increase of up to 50% without changing the outline of the overall assembly.

Each phase in Semikrons SKiiP® X system comprises of 3x3 SKiN modules. In total 27 SKiN modules are used for a 3 phase system.

With the implementation of the new 3D SKiN® the power rating of the same assembly can be pushed far above 2 MW.

Electrical advantages

A further very important improvement comes with 3D SKiN®: Over a large area of the module, DC-plus and DC-minus power traces are placed above each other with minimal distance. This architecture results in a significant reduction of the module internal stray inductance. Compared to the first gen SKiN® designs the internal stray inductance (excluding the terminals) is reduced by ~60% which for the mentioned module sums up to ~1.3nH [5]. Of course the DC terminals add significant stray inductance on top of this, but this also indicates where future generations of 3D SKiN® will go: Eliminating the stray inductance towards the link capacitors allowing for ultra high speed, low loss switching modules and with that also being able to fully leverage new chip technology based on ultrafast switching SiCs.
Stay tuned…

[1] T. Stockmeier, P. Beckedahl, C. Göbl, T. Malzer, “SKiN - Double side sintering technology for new packages”, ISPSD 2011, San Diego
[2] P. Beckedahl, M. Hermann, M. Kind, M. Knebel, J. Nascimento, A. Wintrich, “Performance comparison of traditional packaging technologies to a novel bond wireless all sintered power module”, PCIM 2011, Nuremberg
[3] U. Scheuermann: “Reliability of Planar SKiN Interconnect Technology”, CIPS 2012, Nuremberg
[4] T.Grasshoff, Reinhard Helldörfer, “A Power Module Concept for the Low Voltage MW Class”, Bodos’s Power System® September 2013
[5] P. Beckedahl, M. Spang, O. Tamm, „Breakthrough into the third dimension – Sintered multilayer flex for ultra low inductance power modules”, CIPS 2014 Nuremberg


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