*Simulation model simplifies and speeds topology comparison*

*High power Power Factor Correction (PFC) converters are increasingly important as equipment from welders to uninterruptible power supplies and refrigerators to air conditioners demands powers above 2kW from domestic power supplies.*

*By Cesare Bocchiola, International Rectifier Corp.*

And, while bridgeless and other low frequency PFC solutions may work in equipment such as air conditioners where there is space for large inductors, other applications demand the use of high frequency PFC stages to minimize space and weight.

### Single-stage versus dual interleaved

The options for a high frequency PFC stage are between singlestage or multi-stage (interleaved) boost topologies.

In general, single stage boost PFCs working at power ranges exceeding 1500W can start to show limitations - power switches in the standard TO247 package become critical from a thermal point of view, shunt resistors need to be replaced by current transformers, and inductors become bulky and expensive. In addition, the output capacitor becomes a critical component due to the large amount of current ripple to filter. To address these problems, multi stage – interleaved - boost PFCs are gaining popularity. These claim a number of advantages over a single stage topology including:

a) Reduction of total magnetic core volume

b) Potential EMI filter reduction

c) Reduction of the current ripple in the DC link capacitor (which increases reliability)

Figure 1 shows schematics and idealised waveforms for each topology. In the interleaved topology each stage handles half the converter power and ripple currents are reduced by 180° phase shift between the two PWM signals. While this would be an advantage in boost circuits fed by a DC input voltage, in a PFC design the duty cycle is far from constant during the rectified half line cycle and the ripple current reduction - both in the input and in the output capacitor - is not always evident. Thus, EMI filter, silicon power dissipation and output capacitor ripple minimization are not the automatic result of using a dual stage PFC. This is why designers are looking for ways to accurately compare the benefits of each.

### Mathcad® Models

To simplify this task, International Rectifier has developed a Mathcad ® simulation system that allows very precise comparison between the two alternative solutions and gives the flexibility to change operating conditions so as to identify the optimum topology according to application requirements. The IR system combines a discrete time emulation of actual circuit waveforms, which approximates continuum time functions, together with precise power loss estimations based on power devices models. A full emulation of input current spectrum (achieved by FFT) facilitates comparison of input filter designs to cope with EN55014 limits.

Here the models will be described with reference to a 2000W PFC, and simulation results given for the following operating conditions:

a) Standard European or extended input range, 50Hz frequency

b) Identical inductor values for both designs

c) IGBT power switch (IRGP4068D) and Hexfred diode

d) Single stage Ð input filter

e) Identical switching frequency (40kHz) and output voltage (380Vdc)

Firstly, duty cycle is simulated during the line half cycle. This is the same for both single and dual stage PFC. Current waveforms can then be calculated as a function of application parameters and duty cycle. Figure 2 shows inductor average current, inductor ripple current and valley and peak inductor currents for the single stage booster and for the dual interleaved converter based on 1mH inductor values.

To properly calculate power dissipation in the switch(es) and the diode(s), the time functions are needed as well as the envelopes, while switch currents at valley and peak are needed to calculate Eon and Eoff, the output capacitor’s current and its ESR. Figure 3 shows the simulation of switch currents and ripple current for the single stage converter.

With this information:

a) Switch and diode power dissipation can be precisely calculated, provided the two devices have been properly modelled

b) The magnetic core can be chosen, and the winding designed, allowing estimation of copper and core losses

c) The shunt resistor (which senses IL current for the controller) can be designed, and its power dissipation calculated

d) Output capacitor power dissipation can be derived

For the shunt, a 0.5Vpk voltage is selected, according to the requirements of the IR1150 one-cycle-control® PFC control IC and it is assumed that the designer knows how to choose Cout as a function of the different application requirements including ripple and hold-up time. Cout and ESR are then input parameters to the simulation sheet (in this example, 4 x 470uF/ 400V PEH506 85°C capacitors are assumed, with a total ESR of 160mOhm/4 = 40mOhm).

Please note that, because Vout is considered perfectly constant (no voltage ripple) capacitor current has two main AC components: one at the line frequency (generating the actual voltage ripple, which is neglected) and the second one at high frequency. The final step is to take the FFT of the inductor current over the whole half cycle and compare the spectrum with the EN55014 limits, with the purpose of EMI filter design. To do that, the effect of the line impedance stabilization network (LISN) has to be considered.

The system block diagram including the LISN is shown in figure 4, alongside the inductor ripples for the single and dual stage converters. The input filter is composed of Lf, Cx and Cb. Only differential mode noise is considered here - common mode noise is of marginal interest for PFC topology comparison. The filter has to be designed by iterations: component values are chosen and simulation is run until the line input current EMI spectrum falls below EN limits.

### Practical example

As a practical example let us consider Table 1, which summarises results for simulations of the following designs:

a) 230V input single stage

b) 85-255V input single stage

c) 230V input dual stage

d) 85-255V input dual stage

Standard core sets are chosen for each design, and 2 to 3A/mm2 current density in the inductor’s windings are assumed, with a 40% fill ratio.

It appears that the dual interleaved booster does not offer significant advantage, except reduction of losses into the silicon and the output capacitor, which are more than compensated for by a drastic increase in coil losses!

An alternative design assumes the same inductance for the dual interleaved converter and for the single stage (400uH per inductor); by keeping the same core size, coil losses can be reduced by four, while little or no change can be observed on silicon losses. However, the input filter now needs a 75uH inductance instead of 50uH. In principle, 50% more filter inductance needs 50% more magnetic material, and, for the same total input current, the same winding losses. So total magnetic material increases, but total power dissipation becomes much better.

**Conclusion**

Comparing single stage and dual interleaved boost PFC is not straightforward. There may be advantages and drawbacks in both solutions and the latter is not necessarily a panacea for all designs and/or operating conditions. Using the Mathcad-based simulation tool, designers can more accurately compare the two solutions based on real-life criteria and, thus, choose the optimum topology according to system requirements.