Extending the Limits of Standard Module Technology
U. Scheuermann, F. Ebersberger
Increasing the power density of the standard technology is a continuous challenge in power module development. While single chip packages like hockey pucks are available for very large die sizes, the application of these packages requires a high mechanical and constructive effort. The state-of-the-art technology for high volume phase leg modules comprises a solder connection between a chip and an insulating substrate with bond wire top surface connection and a second solder connection between the populated substrate and a base plate – but this bond wire technology is currently limited to a die size of less than 20 x 20mm². Pushing out these limits to new frontiers is the goal of this investigation. Presenting a semi-controlled input rectifier phase leg module – composed of a thyristor and a diode of 24.3 x 24.3mm² and 22.4 x 22.4mm² chip size, respectively – the challenges with respect to the reliability and lifetime are explored and possible improvements to enhance the classical technology to meet the reliability requirements are presented.
1 Introduction
In the evolution of power semiconductors, the pressure towards increasing current capability and current density are strong driving forces. Standard power modules for medium power applications are today using an established design concept with well controlled production technologies capable of high volume production. These technologies are a solder process to connect a silicon chip to an insulated substrate, as well as the substrate to a metal base plate on one hand and a wire bond process to connect the top side of the chip to the substrate on the other hand.
While for MOSFET and IGBT modules, the task of increasing the current capability can be met by paralleling several chips, this solution cannot easily be adapted to thyristors due to the different switching behavior of this device. So if half- or full-controlled input rectifiers are required for power inverter applications, modules with the necessary current capability suitable for the same assembly platform are needed. A new module standard is evolving these days with a standardized module height of 17mm. For this new technology standard, input rectifiers with the same module height are required to allow compact inverter designs. Therefore, there is a high pressure to push today’s limits of the standard technology towards a chip size above 20 x 20mm² in an insulated power module. This is a challenge for both technologies: the solder process and the bond wire technique, but also for the general architecture of the power module to supply the high currents – especially for the required surge current capability – and to dissipate the heat generated by the thyristor losses.
Fig. 1 gives an image of the module concept of the SEMiX® platform.
Figure 1. SEMiX rectifier (right) compatible to SEMiX® inverter modules (left). Both module families together form a standard construction platform for inverter design.
The rectifier module was developed to match the assembly platform of the already introduced SEMiX® inverter module [1],[2]. Both module families have the same height and spacing for mounting on a heat sink. Both families use spring contacts for control and sensor contacts, which allow a simple assembly process of the driver board on top of the module. For customers, that do not want to mount the driver board directly on top of the module, optional fast-on adapters are available.
2 Challenges in design
When considering the task of increasing the chip size above an existing limit, several challenges have to be met. The CAD-drawing in Fig. 2 shows the module torso without housing to illustrate the following discussion on the major exigencies to develop this module.
Figure 2. CAD image of the SEMiX full controlled rectifier phase leg module for 300A nominal current at 85°C case temperature
2.1 Thermal design
First, the large chip area leads to increasing temperature gradients across the chip surface. The simulation in Fig. 3 shows the temperature gradient for two lines along the chip edge and through the chip center. The simulation model assumed the chip being soldered to a DBC-substrate, which again was soldered to a 3mm Cu base plate. This module model was then assembled on a Cu water-cooled heat sink with a 50μm layer of thermal grease. The heat sink temperature was set to 10°C and a current of 300A dissipated a power of 360W in the thyristor chip. The simulation shows, that the temperature spread in the silicon reaches almost 15°C between the maximum temperature in the center and the minimum temperature at the chip corner. This result identifies the first challenge in increasing the chip size further. Due to the concentration of thermal losses, the gradients across the chip surface are becoming more pronounced with increasing chip size. This phenomenon is one reason for the limitation of the maximum chip size.
It should be noted, that using the temperature dependence of semiconductor parameters of the device itself – as is done by using a calibrated forward voltage drop as a function of temperature – can easily result in an under-estimation of the maximum junction temperature. This technique, which is commonly used with IGBT or diodes, integrates over the junction area and delivers a single value. Investigations on the relation between the maximum junction temperature and the integral value delivered by the forward voltage drop for a small sense current has shown that the integral value is approximately 2/3 above the minimum temperature and 1/3 below the maximum [3]. This would result in a temperature of ~60°C for the integral value, while the maximum is close to 66°C for the example in Fig. 3. This effect will grow with increasing chip size.
Figure. 3. Temperature distribution on the surface of a 24.3 x 24.3mm² silicon chip, mounted in a standard module. Load current 300A, Cu water cooled heat sink.
The infrared camera image in Fig. 4 shows a measurement of a 24.3 x 24.3mm² thyristor chip in a module build up with the same layer system as the simulation model. The IR-image was taken from a torso without housing and soft mould. All surfaces of the torso were sprayed with a powder to ensure that all parts showed a comparable coefficient of emission. It is important to assure an equal emissivity of all surfaces, if a thermal interpretation of the IR-camera image is intended.
Figure 4. IR-camera image of SEMiX® half-controlled phase leg. Load current in thyristor only 300A
The measurement confirms the simulation results in good correspondence. The maximum chip temperature is found to be 68°C, while the corner of the thyristor exhibits a temperature of estimated 50°C.
2.2 High current architecture
The second critical design aspect of a high current bridge rectifier module is to achieve the required current capability of the package. For phase leg modules with lower current capability, a current path on the DBC metallization is sufficient to conduct the current between the minus terminal and the bottom switch. This is not achievable for the continuous current rating of ITAV=300A for the half-controlled or fullcontrolled rectifier module with the 24.3 x 24.3mm² thyristor. For this high current rectifier module a special high current contact is necessary. Fig. 4 had shown already, that even the special connector with a minimum cross section of 1.5 x 5mm² (at the constriction) reaches a temperature of 30-40°C above heat sink temperature for a continuous current of 300A.
Figure 5. Finite element design study on the SEMiX® Rectifier Module with special connector – image shows the exaggerated deformation after solder process.
The implementation of the special connector has a considerable impact on the mechanical behavior of the module. Therefore, its architecture is important for the reliability of the module. Fig. 5 shows one of many design studies performed with finite element algorithms to determine the optimal geometry for the special connector. The image displays the deformation of the module after cooling down from the solder solidus temperature to room temperature. The image visualizes the deformation of the layers due to the differences in the coefficients of thermal expansion, exaggerated by a scaling factor of approx. 40. The ‘von Mises’ stress in the system is also show by coloration.
Figure 6. Finite element design study on special connector - image shows the exaggerated deformation after solder process
The deformation of the special connector after cooling down from the melting temperature of the solder to room temperature is shown in detail in Fig. 6. The design of this special connector shows implemented constrictions, which allow an optimized trade-off between the current capability and the mechanical flexibility to comply with the target reliability and lifetime expectations of the module.
2.3 Surge current capability
The third challenge for the architecture of the rectifier module was the surge current capability of the package. The target value for the ITSM was 9300A at room temperature. To achieve this target, the current path through the power terminals, along the current track on the DBC and through the bond wires has to be capable of handling the high current density.
Critical positions are known to be the track on the DBC metallization and the wire bond layout. The track on the DBC was kept short by implementing the special connector. It provides sufficient cross section for the high surge current. The bond wire layout on the other hand had to be designed carefully to achieve the required surge current capability.
Fig. 7 shows the bond wire layout for the 24.3 x 24.3mm² thyristor in the SEMiX® rectifier module. As marked by the arrows, a very short current path is possible to conduct the current form the negative connector through the wire bonds to the cathode of the thyristor and trough the chip to DBC metallization and to the AC-terminal. This results in a severe current unbalance during surge current test.
This problem was solved by increasing the length of the wire bonds for this chip region and by reducing the number of bond stitches in this area. This does not affect the current distribution under constant current load as can be seen in Fig. 4, but improves the surge current capability considerably.
Figure 7. Wire bond layout of the 24.3 x 24.3mm² thyristor on the bottom position – the red arrows mark the shortest current path.
Fig. 8 shows the surge current characteristic of the 24.3 x 24.3mm² thyristor for a 10ms sine half wave surge current of an amplitude of 9000A, which is close to the specified datasheet value of 9300A at room temperature. The peak losses for this pulse can be calculated to be 72kW.
Figure 8. Surge current as a function of the on-state voltage of a 24.3 x 24.3mm² thyristor during surge current test with 9000A
The temperature evolution during such a high surge current pulse is difficult to measure with an IR camera due to the short pulse length of the load pulse. But since the thermal time constants are much higher in the range of seconds, an IR camera image can give a good approximation of the temperature effect of such a surge current pulse. Fig. 9 shows an infrared image of the 24.3 x 24.3mm² thyristor shortly after the surge current pulse shown in Fig. 8. The display window of the IR image is comparable to that in Fig. 7.
The IR image shows, that the wire bonds – especially the short bond close to minus connector – have a temperature of more than 160°C. Since a triggering of the IR camera was not possible, Fig. 9 cannot be interpreted as the maximum temperature. It represents an image after an undefined period of time after the surge pulse, but it illustrates that the bond wires heat up to above 160°C during the pulse and that they also store the heat longer than other parts as the power connectors.
Figure 9. IR Thyristor Image shortly after a surge current pulse with 9000A
All aspects discussed above lead to the final design as shown in Figure 10.
Figure 10. Torso of the SEMiX® full-controlled rectifier module with two 24.3 x 24.3mm² thyristors
3 Module reliability
After the critical design aspects were solved, the qualification tests were started. For the described architecture of the SEMiX® rectifier module, the temperature cycling and the power cycling test are the important qualification procedures.
3.1 Temperature cycling test
The temperature cycling test is an important procedure to verify the integrity of the package design. The different materials with varying coefficients of thermal expansion (CTE) have to survive ambient temperature changes, which incorporate thermally induced stress in the layer construction. The interfaces have to be geometrically stable enough to withstand the stress conditions.
Fig. 11 shows a scanning acoustic microscope image of the interface between the silicon chip and the DBC substrate (top) and between the DBC substrate and the base plate (bottom) of a SEMiX® rectifier module after production. The interface between the chip and the DBC shows a good solder connection without voids. In the interface between the substrate and the base plate some voids can be observed, but they are small and predominantly at the edge or outside the chip area. Therefore, the thermal path to the heat sink is sufficient to transport the heat out of the system.
Figure 11. Scanning Acoustic Microscope (SAM) image of a new SEMiX® rectifier module:Chip solder layer (top) and substrate solder layer (bottom)
Fig. 12 shows the same set of SAM images after 150 temperature cycles. The cycles were performed in a two chamber test system with -40°C and +125°C chamber temperature.
Figure 12. Rectifier module after 150 temperature cycles -40 +125°C (marked delamination)
The white areas (bottom of Fig. 12) at the substrate edges and especially pronounced in the corners of the substrate show the beginning delamination of the solder interface. This phenomenon is caused by the differences in CTE. But the delamination is found only outside the chip area. The white areas correspond to regions of strong reflection of the acoustic signal. Since the SAM image is taken from the base plate side of the module, the reflection of the signal in the substrate solder interface reduces the signal strength in the deeper layers. Therefore dark areas are found in the depth of the chip solder layer (top image of Fig. 12). These dark areas are found outside the chip area. This is a satisfactory result after 150 temperature cycles, taking into account that 100 cycles are considered as lifetime requirement for these accelerated test conditions.
Comparable results were found for all modules in test and all modules maintained their full insulation capability after the 150 temperature cycles.
3.2 Power cycling test
Equally important for the reliability is the power cycling stability for a power module, because a user of the module expects the module to maintain its performance for a required lifetime. In the power cycling test, the module is actively heated by the losses in chip at the specified maximum nominal current until an upper junction temperature limit is reached, then the load current is turned of until the lower junction temperature limit is attained. This cycling is repeated until the device fails.
Fig. 13 shows a preliminary result of the test, that is currently still in process. The rectifier modules are connected in series. All bottom switches in series are conducting one half-sine wave of a 50Hz AC current, while all top switches are conduction the opposite half-sine wave of the current.
Thermocouples on the chips allow the monitoring of the junction temperature of the chips. Due to the center gate of the thyristors in the device under test (DUT), the thermocouples cannot be placed in the center of the chip and therefore the temperature shown is not the maximum junction temperature. Furthermore, the load current is adjusted in compliance to the data sheet of the module and assumes the maximum allowable thermal resistance of the DUT [4]. The conventional safety margins in the thermal resistance result in a junction temperature below the maximum value.
Fig. 13 shows the junction temperature cycles for the bottom and top switch of a single full-controlled SEMiX® rectifier module with two 24.3 x 24.3mm² thyristors. Two curves show the initial temperature swing and the swing after approx. 4700 cycles. While the top switch temperature swing is almost unchanged, the bottom switch shows a small increase in the maximum junction temperature. The further results of the ongoing test will show, if this increase will continue and exceed the maximum allowable increase of 20% above the thermal resistance initial value.
Figure 13. Power cycling test result after 4700 power cycles for the top and the bottom switch of one fullcontrolled SEMiX® rectifier module.
4 Conclusion and outlook
The presented results have shown, that the conventional technology of standard power modules is extendable to chip sizes up to 24.3 x 24.3mm². By carefully optimizing the architecture of the design, the reliability requirements can be met. Even though, the power cycling test is not finished jet, the preliminary results seem to support the conclusion, that the target can be reached.
For a further increase of the chip size in standard power module architecture, the ribbon bond technology is a promising candidate (Fig. 14).
Figure 14. Investigation of ribbon bond technology to improve current capability and surge current limits.
If the solder technology should be the limit for a further increase of the silicon chip size, the diffusion sintering technology is an alternative with high expectations (Fig. 15).
Figure 15. Thyristor 24.3x24.3mm² – left: after diffusion sintering process – right: after bending over a curved surface
Literature:
[1] Annacker, R.; Grasshoff, T.: SEMiX – A New Platform for IGBT Modules, PCIM Europe 08/2003, pp 46-47
[2] Stockmeier, T.; Manz, Y; Steger, J.: Novel High Power Semiconductor Module for Trench IGBTs, Proc. ISPSD 2004, Japan, pp 343-346.
[3] Hamidi, A. : Contribution à l’étude des phénomènes de fatigue thermique des modules IGBT de forte puissance destines aux application de traction. Dissertation, Grenoble, 1998
[4] Scheuermann, U.; Herr, E.: A Novel Power Module Design and Technology for Improved Power Cycling Capability, Microelectronics Reliability 41/9-10 (2001), pp 1713-1718.
[5] Mertens, C.; Sittig, R.: Low Temperature Joining Technique for Improved Reliability, Proc. 2nd International Conference on Integrated Power Systems CIPS 2002, pp 95-100.
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