Paralleling is a fundamental concept in power electronics application. To estimate the unbalance caused by the variation of parameters of the paralleled elements, a ‘worst case’ consideration is often performed by assuming the combination of elements at the upper and lower specification limit. This approach neglects the probability of the occurrence of such a combination. As an example, the impact of different on-state losses on the DC current sharing is considered. Using measured statistical distributions on the spread of on-state losses for an IGBT and a diode, the ‘worst case’ analysis is evaluated and a proposal for a statistical approach to define a realistic de-rating factor is presented.
The parallel connection of elements to scale the current capability of the single element to an application requirement is a fundamental concept in power electronics. This concept is implemented in IGBT or MOSFET chips, where single MOS-gated cells are connected in parallel to form a modern power chip, it is continued in power modules, where often chips are paralleled to achieve the required current capability and it is further extended when modules are paralleled in high power converters.
While in theory, the parallel connection of identical elements appears simple, severe problems can arise in a practical implementation. The variation of element parameters as well as an unavoidable asymmetry in geometrical arrangement leads to an unbalance of losses between those elements, which can considerably increase the stress for a single element. To avoid the consequence of reduced lifetime and reliability, a de-rating of the maximum current is highly recommended.
Not much detailed information is available on how de-rating factors are determined by application engineers or recommended by power module manufacturers. But at first glance it seems obvious, that the issue of de-rating becomes more important with the number of elements applied in parallel. While paralleling two or three elements seems feasible with little or no de-rating, most application engineers who use heavy paralleling are quite aware of the potential risk.
Often the requirement for specially selected elements for parallel application with a reduced parameter spread is considered as the solution to reduce the risk of unbalanced losses.
This request for specially selected elements has two major draw backs: First, this selection cannot be performed on all contributing parameters. While a selection of diodes in VF-groups is possible, a simultaneous selection for dynamic losses is hardly feasible. Second – and much more important – the process of selection is not compatible with industrial series production, because only a varying fraction of the total production lot will be left after selection, leading to an uncontrolled output and to the question what to do with the unselected rest of the production.
SCOPE OF THE INVESTIGATION
To study the problem of paralleling, we will focus on a practical example. Only a single parameter will be considered in the following investigation: the forward voltage drop of a power semiconductor chip. Even though we are just considering a single parameter, the results are not limited to the special example, but applicable to other parameters and even to a combination of parameters.
A conventional IGBT power module (SKM100 GB123) is selected as a vehicle for our investigation . In a parallel configuration of such a half bridge module, both IGBTs and freewheeling diodes will be operated in parallel. Therefore, both power chips must be considered.
First, an IGBT chip will be analyzed. Since the IGBT has a positive temperature coefficient at nominal current, it is generally considered well suited for parallel connection. Second, a diode chip will be investigated in the same methodology. The diode is usually considered much more critical, since the temperature coefficient of the forward voltage drop is typically slightly negative at nominal current.
WORST CASE CONSIDERATION
For both chip types, the ‘worst case’ consideration will be performed. This consideration assumes, that elements from the specification limits – in our example modules with the maximum and minimum forward voltage drop – will be connected in parallel.
Figure 1. On-state voltage model for freewheeling diode SKCD61C120I implemented in SKM100GB123D – full circles mark data sheet values
To analyze the consequence of this ‘worst case’ selection, the specification of the module must be transformed into an analytical form by expressing the forward voltage drop as a function of temperature and current with an additional scaling factor, which allows to describe the minimum, typical or maximum specification values. A simplified linear characteristic was selected for the current-voltage-characteristics. Fig. 1 shows the forward voltage model for the diode. The ‘worst case’ situation in paralleling occurs, when one module with a forward voltage drop at the lower specification limit (LSL) is selected together with one or more modules with a voltage drop at the upper specification limit (USL).
We assume that no thermal coupling exists between the modules and that the IGBTs and diodes thermal resistances junction-case are given by the maximum data sheet values with 0.18K/W and 0.50K/W, respectively. Further, we assume that the heat sink temperature is fixed to 85°C. These assumptions on the thermal environment are not restricting the basic results of the investigation; different assumptions would only lead to different numerical results.
Now it is possible to calculate the impact of the difference in forward voltage drop on the resulting chip temperatures and the current unbalance. Start parameters are set for the current through each chip and for the temperatures of the low and high voltage drop branch. Then the forward voltage drop is calculated as a function of temperature and current. With this value, the losses can be calculated and the correct chip temperature can be calculated from the thermal model. Now the difference between the assumed and calculated temperature are minimized by adjusting the current through each branch, while the difference of the voltage drop in each branch is adjusted to zero as a boundary condition. This procedure can easily be implemented in an EXCEL spreadsheet using the powerful ‘solver’ tool.
The result is displayed in Fig. 2 for up to 20 modules in parallel and a target current of 75A per module. For the single module (n=1) a specimen at the upper specification is selected to illustrate the ‘worst case’ situation for the case without paralleling.
Figure 2. ‘Worst case’ consideration for the IGBT in a SKM100GB123 module as a function of parallel elements – unbalance in current and temperature
The current per module and the junction temperatures are displayed for the LSL and the USL branch. For two modules in parallel, the current in the LSL branch is already above 90A and continues to increase to >103A, while the current in the USL branch starts at ~60A for two modules in parallel and increases slowly to 73.5A per module for 20 modules in parallel.
The temperature for the LSL branch starts at ~138°C for two modules in parallel and is therefore 4°C higher compared to a single module at the maximum specification limit. It increases to ~152°C for 20 modules in parallel, while the temperature in the USL branch remains below 133°C. Even though, the calculated increase of almost 20°C for the parallel operation of 20 modules will reduce the lifetime of the application, the consequences are not severe and can be compensated by a moderate current de-rating.
Now we can perform the ‘worst case’ consideration for the diode by applying the same procedure. We only have to replace the forward voltage drop model and the thermal model and select a target current of 50A per diode. The result is depicted in Fig. 3.
Figure 3. Worst case consideration for the diode in a SKM100GB123 module as a function of parallel elements – unbalance in current and temperature
The result for the diode is much more alarming than for the IGBT. For 2 modules in parallel, the current of 75A in LSL branch is 50% higher compared to the worst single module within specification limits. And the situation gets worse with increasing number of parallel modules and the current reaches almost 2.25 times the target current for the worst case with 20 modules in parallel.
This unbalance causes a critical distribution of junction temperatures. Starting at 145°C for two modules in parallel, the temperature increases to 190°C for the LSL branch in the ‘worst case’ consideration. This effect is much more severe for the diode as for the IGBT due to the differences in the temperature coefficient. While the positive temperature coefficient for the forward voltage drop of the IGBT is reducing the unbalance in parallel application, the negative temperature coefficient of the diode enhances the unbalance and endangers a heavy parallel operation of freewheeling diodes.
STATISTICAL DISTRIBUTION DATA
The ‘worst case’ consideration has lead to serious concerns with respect to system designs with heavily parallel connected modules. However, some applications are running in practice with 20 or more modules in parallel without the expected serious problems. How can we explain the different perceptions? The answer to this question is found in the statistics. Looking at the ‘worst case’ consideration, we have to discuss the probability of an occurrence of the considered combination. Therefore we need statistical data on the real forward voltage drop distribution of IGBTs and diodes. To evaluate a series production, it is not sufficient to look at the statistical data of just one production lot. For a general statement, it is necessary to take into account the statistical data of several different production lots.
Fig. 4 shows the statistical distribution of the forward voltage drop at ICE=75A comprising of 236,000 IGBT (SIGC121T120R2C) together with the lower and upper specification limits and the normal distribution fitted to the histogram .
Figure 4. Statistical distribution of forward voltage drop @ ICE=75A of 236,000 IGBT chips (SIG C 121 T 120 R2C) – data courtesy of Infineon technologies
On the basis of this statistical data, an evaluation of the probability of occurrence can be applied to the ‘worst case’ consideration conducted before.
Figure 5. Probability of Occurence of the worst case consideration of paralleling IGBTs on the basis of normal chip distribution in Figure 4
The probability of occurrence of a combination is the product of the probabilities for each single selection, if we assume each selection to be independent. The result is given in Fig. 5.
Fig. 5 quantifies the presumption, that can be derived from considering the chip distribution in Fig. 4. The probability of finding one IGBT at the upper specification limit is already very low: only 1 out of 1012 chips will have a forward voltage drop at our above USL. The combination of one chip at the LSL and 9 chips at the USL already has a probability of less then 10-100ppm.
This result is confirmed by the probability review of the diode ‘worst case’ consideration. The statistical distribution in Fig. 6 of a production quantity of 125,000 CAL diodes SKCD61C120I is the basis for the statistical evaluation.
Figure 6. Statistical distribution of forward voltage drop at 1F = 50A @ IF=50A of 125,000 diode chips (SKCD61C120I)
The probability of occurrence given in Fig. 7 is similar to the examination of the IGBT ‘worst case’ paralleling in Fig. 5. The probability of occurrence of a combination of a growing number of elements decreases rapidly. Finding a ‘worst case’ combination with 10 parallel chips with the given specification limits and statistical distribution can be considered impossible.
Figure 7. Probability of occurence of the worst case scenario of paraleling diodes on basis of the normal chip distribution in Figure 6
V. STATISTICAL APPROACH
While the ‘worst case’ consideration results lead to severe concerns regarding the paralleling of chips, the calculation of the probability of occurrence shows that the calculated scenarios are not probable to occur in real application. Therefore, a more realistic statistical approach is calculated by defining a constant probability of the occurrence for each combination of 1ppm as a starting point. On the basis of the given distribution of on-state losses a Lower Calculation Limit (LCL) and an Upper Calculation Limit (UCL) is determined, so that the selection of chips below or above these limits, respectively, results in the defined probability. Since this procedure is not unique, these limits are defined symmetrically to the mean value xm of the normal distribution (xm-LCL = UCL-xm). The method is illustrated for the diode in Figure 8.
Figure 8. The limits LCL and UCL are defined symmetrically to the mean value – chips from below LCL and above UCL are combined with 1ppm probability
Since the probability of occurrence decreases significantly when increasing the number of chips connected in parallel, the limits LCL and UCL have to move towards the mean value of the normal distribution to maintain a constant probability of 1ppm. Now the unbalance generated by the combination of chips outside of the calculation limits LCL and UCL can be calculated.
Applying this methodology for the IGBT results in the unbalance of current and temperature as displayed in Fig. 9.
Selecting the extreme modules for paralleling so, that a probability of occurrence is constantly 1ppm for each scenario, the maximum unbalance of the IGBT for a projected target of ICE=75A per chip is reached for 2 chips in parallel with ~87A. This current unbalance provokes a corresponding unbalance in temperature with a maximum of ~132°C. This is only an increase of 2K compared to a single chip with a high onstate voltage drop at 1ppm probability of occurrence. For an increasing number of parallel chips, this unbalance is reduced for a fixed probability of occurrence of 1ppm until it reaches a completely balanced situation for 20 chips in parallel.
Figure 9. Statistical approach with 1ppm probability of occurrence for the IGBT in a SKM100GB123 module as a function of parallel elements
Even more interesting is the result of the statistical approach for the diode due to the negative temperature coefficient. Selecting the extreme modules with a fixed probability of occurrence of 1ppm as described in Fig. 8, the resulting unbalance can be depicted in Fig. 10.
Figure 10. Statistical approach with 1ppm probability of occurrence for the Diode in a SKM100GB123 module as a function of parallel elements
The current per chip for the LCL-chip reaches its maximum for n=3 at only 64A and then decreases until a complete balance is reached for 20 chips in parallel. The junction temperature reaches a maximum of ~138°C compared to approx. 130°C when selecting a single diode of high on-state losses with 1ppm probability.
While the different approaches result in only a small difference for a single diode – maximum junction temperature is 132.2°C for ‘worst case’ and 130.5°C for 1ppm probability, the calculated maximum temperatures diverge considerably for a growing number of parallel diodes.
VI. DE-RATING FACTOR FOR PARALLELING MODULES
On the basis of the data presented, we can define a de-rating factor for parallel operation, which accounts for the variation of on-state voltage drop of the discussed SKM100GB123D module. Therefore we need to define a maximum temperature that will be allowed in parallel operation. Then the procedure can be recalculated with the additional boundary condition, that the total current through the group of parallel modules is limited by the maximum temperature.
Concentrating on the diode as more critical element due to the negative temperature characteristic of the on-state voltage, we can calculate the de-rating curves for the ‘worst case’ consideration and the statistical approach as shown in Fig. 11
Figure 11. Derating factor resulting from on-state variation for the ‘worst case’ consideration and statistical approach for paralleling Diodes in SKM100GB123D
For the ’worst case’ consideration the temperature was fixed to 132.2°C. This is the temperature for a single diode with the on-state voltage at the maximum specification limit. The maximum current per chip decreases to 80% for two chips in parallel and declines to less than 40% of the rated current for 20 chips in parallel. According to this calculation, 20 diodes of 50A rated current will only be able to carry 400A or 20A per chip. This would make paralleling very unattractive.
In the statistical approach, the maximum temperature of a single diode with a probability of occurrence of 1ppm is 130.5°C. Therefore, this value was defined as the temperature limit. Now, the maximum allowable current is reduced to 88% for 3 diodes in parallel. This is the minimum in the derating curve. For more than 3 modules in parallel, the derating factor is increasing. It even reaches values of more than 100% for more than 10 modules in parallel. This suprising result illustrates the fact, that a fixed probability of occurrence of 1ppm makes it more unlikely to find a combination of severly unballanced onstate voltages in parallel operation with a high number of elements.
The statistical parameter spread of power semiconductor modules is often a matter of concern for parallel application. The frequently discussed ‘worst case’ scenario as a simple approach leads to results, that appear to allow heavy parallel operation in power electronics only at the cost of drastic current de-rating. Requests for a special selection of modules for parallel application are the consequence.
In this theoretical investigation, we have calculated the consequence of the ‘worst case’ consideration for a standard power module. On the bases of the thermal resistance of a conventional power module, the resulting unbalance from the specification range of the onstate voltage of the IGBT and the diode was calculated as a function of modules in parallel.
The statistical approach proves that the risk of unbalanced power losses is over-estimated in the ‘worst case’ consideration. Calculating the probability of occurrence on the bases of measured parameter distributions of IGBT and diode on-state voltage drops over several production lots shows, that the worst case scenario is highly unlikely. The results are much more favorable for paralleling for a fixed probability of occurrence of 1ppm.
While the principal procedure can be applied to any static or dynamic parameter, only the onstate voltage has been selected as an example in our calculation. For a real application, the dynamic parameters are even more important then the static on-state voltage and parasitic effects like over-voltages and internal oscillations are typically the limiting factors in real parallel applications.
It should be emphasized that this is a theoretical study to compare the difference between a ‘worst case’ consideration versus a statistical approach. Since it is limited to the on-state voltage as the only determining factor, the results are only given to illustrate the procedure, they are not valid for real applications without extensions. To qualify a real parallel application, an extensive experimental investigation as demonstrated in  is mandatory.
Especially the de-rating factor in this survey is only given for demonstration purposes, because it only accounts for the static on-state variation. It should also be noted, that the statistical distributions given here are typical, but not ensured by the manufacturers. Even though parallel application of power modules is a challenging task for development engineers, there is a chance to solve the problems and to design successful applications.
 Privat communications Infineon technogies AG.
 R.Schnell, U.Schlapbach, K.Haas, G.Debled, Parallel Operation of LoPak Modules, Proc. PCIM 2003, PC 12.3, pp 295-302.
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