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Posted on 29 June 2019

Performance to Value

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The Turning of the Tide in Power Semiconductors

Power semiconductors are not new. Indeed the applications where they are typically used are well established. However, what is changing rapidly is the rate of power semiconductor adoption. Fifteen years ago a power electronics based SMPS for your television, video recorder or laptop computer was considered ‘high-end’. A car filled with wafers of silicon to control its electric motor was ‘emerging’ while a wireless charging system for your iPhone was the stuff of science fiction films!

By Benjamin Jackson, International Rectifier, El Segundo

 

So what has changed – did the MOSFET and IGBT technology suddenly get markedly better, well not really. For sure the Rds(on) of a MOSFET today is considerably lower than it was 15 years ago but that does that mean that the MOSFET can be used in applications which were previously out of bounds for power semiconductors. So what was the key to take the power semiconductor from niche to main stream? As with so many new technologies the main limitation is not so much the limited capability of the new technology but more the dominance of the incumbent technology. The value of the traditional solutions was just too high. In the last 10 years this has changed and moreover power semiconductors are now the preferred option. But what are the technical steps which are accelerating this change?

Equation 1 -Value equals performance divided by System Cost

For the last 30 years the power semiconductor companies have been chasing along one axis: performance. In order to make the MOSFET easier to drive the gate charge needed to come down. In order to make the heat sinking manageable the Vce(on) and Rds(on) needed to be lower. All this was aimed at increasing the value proposition of the power switch by giving it more performance. Indeed this exercise was necessary to ensure that the power semiconductor was technically competitive against the traditional solution. However there is another axis which is now being pursued – how cost effective the power semiconductor solution is. So how are semiconductor companies addressing the lower half of our value proposition equation? One way would be through further cost effective manufacturing and indeed this has a role to play, but perhaps more important is making the power switch itself more efficient and no better example than the standard MOSFET and its Rds(on).

Remembering that MOSFET is made up of thousands upon thousands of cells, and the more cells that are placed in parallel the lower the Rds(on) it is easy to make the connection between the on resistance and the MOSFET’s area, or die size as it is commonly known. Figure 1 shows the difference in current flow between a planar and trench MOSFET it can be seen that with the vertical path in the trench design the structure is inherently more efficient at packing more cells together in a small space than planar structures and thereby reducing the Rds(on).

Current flow through planar and trench MOSFETs

This property allowed a smaller die to be used in a trench technology for the same Rds(on) than a planar technology. More commonly known as ‘die shrinking’ this practice enables successively better silicon technologies to achieve the same on resistance in a smaller die size and thereby at a lower die cost. However there are two limitations of die shrinking. Firstly the finer pitch and increasingly complex trench structures usually cost considerably more to make, so while the die size may go down the per unit area cost of the wafer is going up. Inevitably semiconductor manufactures aim for trade off where the die size reduction more than offsets the extra cost per unit area, but this implies you can carry on making the die smaller and smaller albeit with more costly technologies. And herein is the second and more fundamental limitation which is particularly pronounced in power semiconductors.

Power is the key word and Equation 2 shows the factors which limit the power dissipation in a power MOSFET.

Equation 2 shows the factors which limit the power dissipation in a power MOSFET

Where Pd is the power dissipated in the semiconductor switch, Tj is the junction temperature, TA the ambient temperature and RthJA is the total thermal resistance from junction to ambient. Linking power dissipation to current through the MOSFET (3) and then substituting 3 into 2 we end up with the relationship in Equation 4.

Equation 3

Equation 4

Equation 4 shows that the power handling capability is limited by the Rds(on) and the junction to case thermal resistance. With the new technologies we have successfully reduced the on resistance, but by going to smaller and smaller die the thermal resistance increases and thereby limits the current handling capability. In addition we must also consider how the current gets in and out of the die – through wire bonds – Figure 2 shows a typical arrangement.

An example of wire bonding inside a power semiconductor device

Naturally to carry a given current the wires must be of a sufficient diameter to avoid excessive heating and ultimately to prevent fusing. At the same time there must physically be enough room on top of the silicon to attach the bond wires. This combined with the thermal limitations of smaller die mean that the practice of ‘die shrinking’ for power switches is becoming more and more challenging and perhaps soon to reach a fundamental limit. Investing in incredibly complex semiconductor structures to enable the die shrink is a case of diminishing returns. What is needed now however are simpler and more cost effective semiconductor structures and more scrutiny on refining what we put around the semiconductor namely the packaging which limits both the thermal and on resistance performance of the device.

In the automotive power electronics industry there is no better example of the constraints that a package puts on the silicon by looking at a state of the art 40V D2Pak MOSFET. Today the very best of such devices have a maximum Rds(on) of around 1mOhm however of this value around 50% of the Rds(on) can be attributed to the wire bonding and the package. This is a significant impedance to the value of the device, after all the majority of the expense of such devices is in the silicon and not the package. Indeed when 5mOhm was considered advanced technology 0.5mOhm of extra resistance in the package was not an issue – today the picture has changed dramatically. Therefore it is possible to see some clear examples of how reducing the thermal and electrical resistance of the package can deliver far better value and use of the semiconductor inside.

The TO-262 is a well-established power package (see Figure 3) which is widely used in many power applications, particularly those where the power devices are placed on a high performance thermal substrate such as IMS, separate from the control board. The advantage of this assembly is that very good thermal performance can be achieved; the disadvantage is the associated electrical performance of the leads and the mechanical challenges in mass production.

Limitations of the existing TO-262 package.

As shown in Figure 3 the leads of the TO-262 actually add around 1mOhm in addition to the RdS(on) max that is specified on the data sheet. When considering a popular 2mOhm MOSFET in such a package this would mean that the total resistance at the end of the leads would be 50% higher. While the electrical impact of this can be accommodated in the design of the system the joule heating of the leads and the associated reliability concerns at high currents is not as easy to asses. Furthermore due to the wire bonding configuration inside the package the maximum current handling capability is limited along with the Rds(on) performance. To this end International Rectifier set about to understand how more value could be achieved with this well established package. The new WideLead is the result and shown in Figure 4.

Enhanced performance with the new WideLead TO-262 Package

As can be clearly seen in in Figure 4 while the fundamental footprint, overall form factor and construction of the WideLead remains the same as a traditional TO-262 it has, as the name suggests, significantly wider leads! This might appear to be an obvious or even trivial step, but the results on performance are significant. At a first pass by greatly increasing the cross sectional area of the leads the lead resistance was slashed by 50% to around 0.5mOhm. This instantly allows a customer in a through-hole assembly to access more of the performance of the silicon. At the same time the packaging designers did an overhaul of the internal lead frame design, enabling an improved wire bonding configuration to be accommodated. This has the benefit of firstly increasing the maximum current rating of the package from 195A to 240A and at the same time reducing the electrical resistance between the die and the outside of the package – thereby reducing the Rds(on) by up to 20% for the same MOSFET die! Figure 5 compares and contrasts some of the key data sheet parameters for the standard and WideLead versions of these AECQ101 grade components.

Comparison of electrical performance between identical die housed in standard TO-262 and the WideLead TO-262 Package

Comparing the performance on paper and in an application setting however are two very different things. To this end the AUIRF1324L (standard TO-262) and AUIRF1324WL (WideLead) – both with identical silicon were put on an identical test. Varying levels of current were run through the parts for extended periods of time and the lead and junction temperatures measured. Figure 6 shows the results of the evaluations. It can be clearly seen that the WideLead part runs cooler, in fact at a 60A current the WideLead was around 39% cooler than the standard TO-262, the lower resistance in the leads and wire bonds generating less heat in the part. At a system level this offers the benefit of either being able to reduce the size, cost and weight of the cooling arrangement or perhaps enable a lower thermal grade of PCB material to be used for a given current while at the same time reducing conduction losses and improving efficiency. Alternatively by playing the graph horizontally it can be seen by taking a fixed operating temperature of say 120°C a 30% higher current can be achieved with the WideLead, again due to the revised wire bonding inside the package and the lower lead resistance courtside of the package. In both cases the silicon is the same so by improving the package the overall value of the existing silicon is greatly improved. The device is more efficient.

Comparison of performance between two identical MOSFETs accommodated in different packages; the standard TO-262 and the new WideLead TO-262.

At this point it is worth remembering that nowadays an increasing majority of designers choose surface mount components for the easy of manufacture and design. One of the innovations here is the bond wireless Automotive DirectFET package. The benefits of this package have been well documented, but with increasing adoption more system level data for this package is now available in particular comparing it to the standard D2Pak. Be eliminating the bond wires the DirectFET achieves three fundamental system level benefits:

. Very low parasitic inductance
→reduced ringing and excellent high frequency performance
. Very low package resistance
→reduced conduction losses and improved efficiency
. Ability to cool the package from top and bottom
→flexible assembly, reduced thermal resistance

One automotive example of Automotive DirectFET at work is in an inverter such as an electric power steering system, fuel or water pump or cooling fan applications traditionally dominated by the D2Pak and DPak packages. However in the DirectFET by eliminating the wire bonds the value of the silicon is unharnessed. Firstly the 0.5mOhm package resistance of the D2Pak is considerably higher than the 150μΩ which the DirectFET package contributes to the Rds(on) and secondly by freeing up the space on top of the die (traditionally used for wire bonding) the part can be cooled through the top side via thermal interface material directly to a heat sink. This has the benefit of not having to pull the heat through the PCB on the way to the heat sink as is necessary with a D2Pak (see Figure 7).

Comparison of cooling arrangements for a DirectFET and D2Pak

To evaluate the performance of the two configurations two identical 3 phase inverters were constructed, one accommodating various sizes of 40V DirectFET devices from 1.9mOhm to 1mOhm maximum Rds(on) and the other with a 40V 7 pin D2Pak package (AUIRSF3004-7P) with an Rds(on) max of 1.25mOhm. The boards were run at various currents and the junction temperatures of the MOSFETs were measured – Figure 8 shows the results of how Tj varied over time.

Comparison of junction temperature of inverters based on D2Pak-7P and DirectFET devices

The difference between the top side cooled DirectFET and the 7 pin D2pak (cooled in the traditional manner through the PCB – see Figure 7) is clear. A significant difference in performance attributed purely to the Rds(on) and conduction losses would be expected between the 1.25mOhm D2Pak-7P and the 1mOhm AUIRF7739L2 DirectFET. However the true demonstration of the advantage of cooling through the top side of the part is shown when comparing the AUIRF7737L2 (1.9mOhm max) with the D2pak-7P. Despite the AUIRF7737L2 having an Rds(on) that is over 50% higher than the D2Pak-7P the part runs cooler. This offers several benefits; primarily the higher Rds(on) and therefore the more cost competitive DirectFET can be used in place of the D2Pak-7P. At the same time the DirectFET also has a 60% smaller footprint than the traditional package and by cooling through the top of the package and not through the PCB, both sides of the board can be used for components. Alternatively higher current and power could be achieved for a given operating temperature, this can be hugely beneficial in an automotive environment where space and weight are confined and where the new electric systems are competing with traditional engine driven systems which typically have a very high power densities.

Power semiconductor manufacturers will always strive to improve the performance of the semiconductor, but the examples shown here highlight how what goes around the device can make a huge difference in terms of performance, cost and ultimately value. In the early days of power semiconductors much fanfare was given to the efficiency savings which a power electronic solution could bring against a traditional solution. Today with device performance at a level that satisfies many demanding applications the emphasis must now shift to simplify and refine the semiconductor and packaging technology. Ultimately this will improve the efficiency of the system but more over the goals has to be to deliver better value by improving the efficiency of the of the power semiconductor switch itself.

 

 

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