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Posted on 07 October 2019

Power Block Innovations Enhance Synchronous Buck Converters

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Dual MOSFETs in PQFN packages, containing optimized synchronous and control MOSFET devices, enable designers to enhance the efficiency and power density of synchronous buck converters. A new evolution of the dual PQFN package featuring a single-clip connection to both MOSFETs, called power block, introduces an innovative internal structure that further increases efficiency while also helping improve EMI performance and enhance reliability

By Steve Oknaian, International Rectifier Corporation

Synchronous Buck Design and Optimization

As energy efficiency becomes an increasingly important consideration in the design of networking and communications equipment, such as servers, storage, routers, switches and base stations, engineers have adopted synchronous buck converters to increase the efficiency of the power system. Point-of-load converters are examples of such systems.

Unlike a conventional buck, the synchronous buck converter utilizes a MOSFET (synchronous FET) in place of a conventional freewheeling diode. Due to zero voltage switching of this synchronous FET and its low on-state voltage drop, switching losses and losses due to high voltage drop of the conventional diode are eliminated.

To help streamline design, semiconductor vendors have positioned newer families of pairs of devices, optimized for control and sync FET sockets, which allow designers to take advantage of advanced high-efficiency packages such as Power Quad Flat No-lead (PQFN) in various sizes such as 3x3mm, 4x5mm, or 5x6mm. Examples include IR’s IRFH4234 and IRFH4210D in PQFN 5x6, for control FET and sync FET application respectively. These devices feature low gate resistance and Miller charge, for use as the control FET, and ultra-low on-state resistance required of a sync FET, and an integrated Schottky diode displaying low conduction and reverse recovery losses.

Moreover, dual devices combining both the control FET and sync FET in a single package now enable engineers to further simplify circuit board designs and build smaller converters offering greater power density. Many power semiconductor manufacturers offer dual PQFN devices.

Dual MOSFET Package Design

In a conventional dual PQFN package, the sync and control FETs are placed side by side with the drain connections both facing down and connected directly to exposed drain pads on the leadframe (LF) underside. The source connections on the top side of each die are connected to the leadframe source pads via copper clips. Figure 1a illustrates the cross section of a two-clip dual PQFN package. Although the copper clip technology enhances thermal performance compared to more mature package technologies, such as dual SO-8, typical two-clip devices do not have optimum pin-outs for minimizing system parasitic inductance and are not economically structured for optimal heat dissipation.

Conventional two-clip dual PQFN package construction featuring individual clips connected to sync MOSFET and control MOSFET

IR’s new family of power block devices utilizes a proprietary single-clip dual PQFN package, as shown in figure 1b, which overcomes these disadvantages. By connecting the control FET (HS MOSFET) source and the sync FET (LS MOSFET) drain with one clip, this package architecture improves performance and minimizes package parasitics. By allowing the source connection pad of the sync FET to be positioned closer to the drain connection pad of the control FET, the single-clip package achieves optimum input bypassing between input and ground of the synchronous buck circuit. This patented [1] implementation of the sync buck FET combination in one package has been implemented in IR’s portfolio since 2006, originally in iPowIR products and more recently in IR’s award winning PowIRStage products.

Advanced single-clip dual PQFN package

The key to realizing these improvements lies in flipping the sync FET such that its source is in contact with the leadframe. In addition, to further reduce the effect of the overall package/parasitic inductance on switch-node ringing, and so allow faster switching, a separate source connection links the control FET to the gate-driver return. This additional source connection eliminates the adverse effect of common source inductance on the switching performance of the control FET. Common source inductance is defined as the inductance shared by the gate-driver current path and the main power transfer path. It can be a combination of the package inductance and/or PCB trace inductance. In a synchronous buck topology, the high-side MOSFET is hard-switched. With hard-switching, the switching loss is proportional to the turn-on and turn-off time intervals. Increasing turn-on and/or turn-off time will increase the converter's switching losses.

Control FET common source inductance in a synchronous buck converter

The control FET common source inductance, represented by Q1 LS in figure 2a, increases the turn-on and turn-off times. When the control FET is trying to turn on, the drain-to-source current in the control FET increases, and a positive voltage (VLS) proportional to the rate of MOSFET current increase is induced across the common source inductance. This induced voltage reduces the effective gate-to-source voltage, which slows down the MOSFET turn-on. During turn-off the rate of MOSFET current increase is in the reverse direction, which induces a negative VLS voltage across the common source inductance that effectively prevents the control FET from turning off quickly.

The additional source connection provided by IR’s power block devices eliminates the effect of common source inductance, thereby improving switching performance, by allowing the gate-driver voltage to be applied directly to the source bypassing the connection through the package and the PCB. This source connection is highlighted in figure 2a.

IR power block bottom view

Figure 2b shows the bottom view of IR power block. It is pin 2 (Q1S) which is designated for connection to the driver return.

Figures 3 and 4 illustrate the effectiveness of the source sense connection by comparing the switching waveforms and efficiency achieved with and without the source sense. Figure 3 shows that the switching time is shorter when the source sense wire is connected, while figure 4 shows a significant improvement in efficiency when the system is operated with the source sense connection.

Switch-node waveform comparison with and without source sense connection

Efficiency comparison with and without source sense connection

Optimized Pin-Out The pin-out configuration of IR’s power block family allows the designer to minimize the input bypass current path, thereby reducing the parasitic inductances associated with the MOSFET package and PCB traces. This greatly reduces switch-node ringing caused by res- onance between the parasitic inductances and the MOSFET's output capacitance, enabling the designer to meet system EMI requirements, improve thermal management and select devices having lower breakdown voltage.

From the thermal management point of view, the single-clip package allows the synchronous FET source to be in direct contact with the PCB, creating a path of low thermal impedance for optimal heatsinking.

Electrical comparison: efficiency of conventional two-clip package vs IR’s single-clip power block

Figure 5 shows the effects of the single-clip package on electrical and thermal performance by comparing single-clip and conventional two-clip devices containing control and sync FETs with identical parameters. Since the MOSFETs are identical, any differences in performance are due to the package design and the pin-out. The performance of the single-clip device shows a striking advantage over the conventional two-clip dual-MOSFET package, boosting efficiency by as much as 1% while also reducing the operating temperature by 13°C.

Conclusion

The internal structure of the single-clip dual PQFN power block allows the source pad of the sync FET to be positioned between the input and switch-node pads resulting in improved bypassing, reduced electrical losses and increased thermal performance. In addition, the unique return connection pin from the low-power control FET source to the driver enables increased switching speeds. IR’s power block devices in this package, containing pairs of MOSFETs optimized for synchronous buck applications, are being used in a variety of single output and multiphase applications to improve performance, efficiency and reliability.

[1] Christopher Schaffer, “High power MCM package” US Patent No.: 6,946,740,B2, issued Sep 20, 2019

 

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