Posted on 01 November 2019

Power-Save Mode Principles in Low-Power Synchronous Buck Converters

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As with many engineering problems, there is no single best answer

Modern synchronous buck converters for portable applications provide so called powersave mode operation to maintain high efficiency over the entire load range. At light loads, the converter operates with pulse frequency modulation (PFM mode) providing automatic transition into pulse width modulation (PWM mode) at medium to heavy loads.

By Christophe Vaucourt, Portable Power Systems Engineer (MGTS), Texas Instruments


This topic discusses different PFM mode techniques used in modern buck converters such as single threshold PFM regulation scheme and current controlled PFM operation.

In applications requiring fast load transients out of light load operation, the load transient response of the buck converter can be improved with the help of features like fast PFM mode or dynamic voltage positioning.


Figure 1 shows a simplified schematic of a buck regulator featuring the high-side PMOS switch (Q1) and low-side NMOS rectifier (Q2). Each MOSFET also includes a back-gate diode as shown in the diagram.

Simplified Synchronous Buck Converter

A buck converter operates by applying a fixed frequency pulse width modulated (PWM) waveform to an L-C filter. The filter then averages the PWM waveform, resulting in a DC output voltage. For highest efficiency considerations, low voltage DC/DC converters are generally using synchronous rectification (SR) schemes, refer to Figure 1.

To begin a discussion of DC/DC converters, a few fundamental relationships need understanding. In an ideal (lossless) buck converter, the input voltage and the duty cycle of the switch determine the output voltage.

Equation 1

Where the duty cycle is defined as the ratio of the main switch ON time to the total period. This relationship holds as long as there is continuous current flowing in the inductor.

The next step is to follow the operation of the circuit for one switching cycle. In a first step, the PWM signal turns on the main switch (Q1) and the inductor current transitions from the SR (Q2) to the switch (Q1). The current flows from the input capacitor via the high-side switch (Q1) through the inductor into the output capacitor and into the load. To close this loop, the current returns back to the input capacitor. During this phase, the current in the high-side switch (Q1) and the inductor ramps-up until the high side switch is turned off.

In a second step, the PWM signal turns off the main switch (Q1) and the inductor current transitions from the switch (Q1) to the SR (Q2). The current still flows from the inductor into the output capacitor and into the load, but it returns back through the low-side MOSFET rectifier (Q2). The inductor and rectifier current will ramp down. During the rectification cycle, the input capacitor is charged-up.

Another important relationship relates the inductor value to the amount of AC ripple current in the converter.

Equation 2

Where ΔIL is the peak-to-peak ripple current in the inductor.

PWM, Inductor Ripple Current vs. Duty Cycle, Input Voltage

Notice the effect the input to output voltage differential has on the result. The inductor ripple current decreases with higher inductance and increases with higher VIN or VOUT.

Normally, it is advisable to operate with a ripple of less than 30% of the average output current. Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability.


In modern low-power DC/DC regulators, when Power Save Mode (PSM) operation is enabled converters are automatically turning into PFM mode regulation under light load condition.

During PFM operation, the Switched Mode Power Supply (SMPS) is kind of in sleep mode. Only the internal reference and a low quiescent current comparator are enabled to supervise the output voltage, a nonlinear control scheme is applied.

Most of the other functions of the DC/DC converter are turned-off, thereby reducing dramatically the quiescent current consumption down to c.a. 15 to 20uA. Once the output voltage falls below a certain threshold, the DC/DC converter gets up and operates until the output voltage is within its regulation limits.

PFM operation is primarily aimed to increase the DC/DC converter’s efficiency under light load conditions. But as a side effect, it has influence on two major parameters of the DC/DC converter:
- output voltage ripple
- switching / burst frequency

Different control schemes can be used to implement a PFM operation into buck regulators.


Modern regulators aim not only to provide state-of-the art electrical performance but also small solution size. To address these requirements, new high switching frequency converters operating at a nominal fixed frequency of 3MHz have been developed. These new topologies are reducing the value of the external components to 1μH for the inductor and 4.7μF for the output capacitor.

During PWM operation, the converter uses a unique fast response, voltage mode, controller scheme with input voltage feed-forward. This achieves “best-in-class” load and line response and allows the use of tiny inductors and small ceramic input and output capacitors. Furthermore, the converter operates always in continuous conduction mode. This means, that for low output currents, the inductor current will become negative.

Two conditions allow the converter to enter the power-save mode operation:
- the output voltage is larger than the “Comp_Low” level.
- the inductor current has become zero for a min. amount of cycles in a row.

The converter leaves power-save mode when the output voltage drops below the “Comp_Low” threshold (1.5% below the nominal output voltage). As a consequence, the average output voltage is slightly lower than its nominal value in the power-save mode operation. The number of pulses the converter does in power-save mode is dependant on the load, input / output voltages, delay of comparators, output capacitance, etc., and can’t be calculated easily.

In order to minimize the quiescent current whilst in power-save mode (c.a. 90μA), only the reference and the comparator to detect the “Comp_Low” level are kept active. Notice that the Fast-PFM control loop is actually using the “PWM inner modulator” to regulate the output voltage. This way the converter can show excellent transient response during large load swings (i.e. in- and out- of power-save mode).

Fast Response Regulator Block Diagram

FPFM Principle

FPFM Efficiency


During light-load conditions, the TPS62350 converter includes a Fast PFM mode to enhance efficiency whilst to compromising on the transient performance. The regulator transitions smoothly between PWM and FPFM modes with no glitches on its output.

Fast PFM (FPFM) mode offers the excellent transient response performance during large load swings, at the expense of the ultra-light load efficiency (i.e. sub 10μA). Light PFM (LPFM) mode features lower quiescent current (c.a. 30μA), reduced output ripple voltage giving-up a bit on transient performance.

In light PFM mode, the converter only operates when the output voltage trips below a set threshold voltage (i.e. nominal output voltage). It ramps-up the output voltage with a single or multiple pulses and goes back into power-save mode. As a consequence in power-save mode, the average output voltage is slightly higher than its nominal value in PWM mode. This dynamic voltage positioning principle helps to anticipate the instantaneous negative-going transient that will occur when the load is suddenly stepped higher.

Single Pulse, Variable Peak Current PFM Principle (Light PFM)

In order to provide a seamless transition between PFM and PWM modes, the PFM inductor peak-to-peak current has to be larger (c.a. +30% +50%) than the PWM ripple current. For this reason, the inductor ripple current (in LPFM mode) has been made proportional to the input voltage.

The PFM inductor peak switch current can be calculated:

Equation 3

The N-channel rectifier is turned-on and the inductor current ramps down. As the inductor current approaches zero, the N-channel rectifier is turned off and the converter enters a sleep mode, reducing the quiescent current to a minimum.

The principle of the inductor voltage-second balance can be used to derive the PFM timings:

Equation 4

The charge provided by the inductor pulse and the charge supplied by the output capacitor (COUT) to the load should be equal within a single period to maintain a stable DC output voltage. Therefore the PFM burst frequency is determined by:

Equation 5

LPFM Frequency vs. Load Current

 LPFM Efficiency vs. Load Current

Because of the charging balance of the output capacitor needed to maintain a constant value for the output voltage:

Equation 6

Where ΔVOUT is the ripple across the output capacitor. Notice that a single pulse scheme is the PFM principle that produces the lowest output ripple.

It is possible to further reduce the output voltage ripple by: selecting larger value output capacitor. lowering the inductor PFM ripple current. This is only practical in applications with load current guaranteed to be less half the PFM peak-to-peak ripple current, and which do not require the auto-mode transition functionality.


During power-save mode operation the device achieves highest efficiency by reducing its quiescent current consumption. DC/DC converters shut-down most of their control circuitries during dead times. As side-effect of this technique, the device can not be biased-up infinitely fast and need time to “wake-up”. A large load transient (i.e. from light to heavy load condition) causes the output voltage to droop, as the load has to be momentarily supplied by the output capacitor.

To minimize transient voltage drops, a new principle called “Dynamic Voltage Positioning” has been developed.

“Dynamic Voltage Positioning” regulates the output voltage in PFM mode slightly higher than the nominal value (PWM mode). The output voltage is set higher in the magnitude of 1% typ, thereby giving additional headroom to minimize the absolute voltage sag.

Dynamic Voltage Positioning in PFM Mode

In addition to the “Dynamic Voltage Positioning” principle, another technique can also be employed to improve the transient performance.

Fast-PFM mode helps to shorten the wake-up time of the inner regulator circuit. At the expense of larger quiescent current consumption (e.g. 90µA), the activation time can be dramatically reduced.

Figure 10 shows the load transient performance of a Fast-PFM scheme (TPS62350).

Fast-PFM Load Transient Response


In practice, some designers of portable systems try to avoid designs with variable-frequency converters because of the concern about EMI or other aspects related to variable-frequency operation. In some cases, these concerns are valid due to the interaction of PFM converters with sensitive subsystems elsewhere in the portable product. However, PFM architecture offers real benefits.

Single threshold PFM schemes certainly help to achieve low output ripple voltage (vs. older dual thresholds PFM architectures). On the other hand, features like fast-PFM mode rather target application requirements going for tight load transients along with extremely small passive components.

TI continuously drives forward the development and optimization of PFM techniques to achieve best performance on key parameters such as output ripple voltage, quiescent current and load transient response.

As with many engineering problems, there is no single best answer but a range of application specific issues that need to be considered.



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