*A new Verilog model for design*

*Thanks to their cost effectiveness and high performance, LDMOS devices are widely used in radio-frequency applications, ranging from digital communication infrastructure (cellular base stations) to low-cost portable radios (private mobile radios), commonly known as Walkie-Talkies.*

*By Amedeo Michelin Salomon and Giuseppe Privitera, STMicroelectronics*

To reduce the design cycle time and cost for wireless applications it is useful to have models that can help RF Engineers predict and simulate the behavior of RF Power Transistors.

The model introduced here describes with good approximation dc, small-signal Sparameter and large-signal behavior. This model has been implemented in the Agilent Advanced Design System, in Verilog Language.

In this article we will briefly describe how to extract the model parameters for the PD54003L-E device. As an internally unmatched device, the PD54003L-E can be used in various portable applications over HF, VHF and UHF frequency bands. At the end of the article we will validate this new model using ST’s DB-54003L-175 demoboard, especially designed for 2-way portable radio applications using PD54003LE over the 135-175 MHz frequency band.

### Model description and parameter extraction

The model introduced in this article is a behavioral model with the equations written in VERILOG language.

By observing the equivalent model schematic of Figure 1, the following elements can be noticed:

· Parasitic elements associated with the device

· Nonlinear current generator

· JFET resistance

· Substrate-body diode

### Parasitic elements

To model the parasitic elements of the device, a resistance and an inductance are placed in series at each terminal. The model can change the resistance and inductance values according to the simulation temperature.

### Nonlinear current generator

The nonlinear current generator controlled by Vgs and Vds is the most important factor used to calculate the static and dynamic current of the device. Moreover, the static current is required to define the working region of the MOS.

Table 1 reports all the parameters required to extract the equations of the current generator. To get the generator current equation, a set of equations must be defined. An important parameter to consider is the threshold voltage of the device shown in Formula 1.

Moreover, a new threshold voltage formula is necessary to describe the weak and strong inversion region in a single equation (Formula 2).

To describe both regions, a new gate voltage can be defined, as in Formula 3. Another important parameter to define is the gain factor with zero bias. Referring to Formulas 4, 5 and 6, the gain factor degrades according to the Vgs voltage (mobility degradation). Formulas 7 and 8, which define the drain saturation voltage, complete the set of equations needed to define the generator current (Formulas 9 and 10). The automatic ADS optimizer was used to extract the parameters for the current generator using input characteristics and transconductance parameter. L is the physical channel length of the MOS, while L0 influences the output conductance which depends on KE and EPS. DEL and DELVG affect the VD_{SAT} and are extracted from the output characteristics in the saturation region. All the equations have been implemented in VERILOG language.

### JFET resistance

The quasi-saturation region is modeled by a nonlinear JFET resistor. The mathematical empirical equation is defined in Formula 11(using the right hand function approach) (Formula 12), where pres depends on the current and on the drop voltage across Rj. The function g(pres) was created to bind the Rj to the current Id. This is accomplished by introducing a new parameter linked to the dissipated power on Rj (Formula 13), where pres is linked to the dissipated power on Rj through RPWR. Rj is extracted from the dc output characteristics in the linear region with high bias current.

### Substrate-body diode

The body-substrate diode is employed to describe the breakdown, the drain current leakage and the capacitance between the drain and source. The diode current is implemented in Formula 14, 15, 16, 17 and 18. The charge equation is given by Formula 19. The remaining model parameters are the capacitances Cgs and Cgd of the MOSFET. The gate-source capacitance is modeled with a constant capacitance, because it is related to a highly doped MOSFET (Formula 20). Moreover, the gate-drain capacitance can be considered as a classic MOSFET model capacitance, where the equations of the charged capacitance can be divided into four regions. To extract the capacitance variables, a classic configuration has been used to measure the Ciss, Coss and Crss.

### Package simulation

To include all the parasitic elements of the package in the model, several electromagnetic simulations were performed. The simulated package (PowerFLAT), including the internal structure of the device, takes into consideration the leads, the paddle, wire bonding and the pad on the silicon. To minimize the simulation time and increase accuracy, the structure was split into two parts (drain and gate). In this way, the reciprocal coupling between the input and output parts are not considered. To take into account such effect, an extra capacitor (Cgdpackage) has been used. To complete the package model an extra inductor (Lvia) associated with the source has been added. This inductor represents the effect created by the “via holes”. Moreover, using the measured S-parameters of the packaged device, it was possible to extract the Cgd-package and the Lvia. Observing Figure 1, it is possible to see the circuit representing the union between the package model and the device model.

### DC and RF small signal validation

Figure 2 compares the measured with the simulated RF small signal S-parameters.The simulations predict with good approximation the S21 and S22 which are the most difficult to predict.

### Large signal validation

Using the ADS with Harmonic Balance engine simulator, the model has been simulated in conjunction with the dc network and the input and output matching network of ST’s demo-board DB-54003L-175 (Figure 3). The DB-54003L-175 demo-board was developed to demonstrate the best broadband performance of PD54003L-E. Figure 4 compares the simulations and measurements of the demoboard at 155 MHz.

### Conclusions

The described model is suitable for use in all simulation types, ranging from dc to large-signal analyses. Furthermore, the model shows a good robustness in terms of convergence. Such robustness is given by the good approximation of the device model in the quadratic and saturation regions.

Thanks to this new Verilog model, customers will now be able to predict and simulate the behavior of STMicroelectronics RF DMOS and LDMOS products, reducing design cycle time and time to market.