Integration of 1200V SOI gate driver ICs into a medium power IGBT module package
A novel approach for medium power IPMs is presented combining a 1200V, 50A IGBT/FWD-Inverter module based on spring contact technology with new developed advanced silicon on insulator (SOI) gate driver ICs in a reliable cost effective package with excellent thermal resistance. The measurement results (static, dynamic and three phase power inverter tests) demonstrate the driver and system performance. The new system approach for industrial standard drive applications supports the market trend towards integrated power module solutions already known from the low power consumer market.
Intelligent Power Modules (IPM) with fully integrated solutions which combine both driving circuitry and power bridges in a compact and robust package are restricted to low power applications (600V, 1200V, ≤35A)  . To develop the medium power market the extension of the current range of the IPMs from 35A up to 100A or even higher is necessary. This requires on the one hand larger system packages with lower thermal resistance at the same high flexibility and on the other hand gate drive ICs with higher output currents and higher ruggedness against system noise. An IPM solution for medium power applications (1200V, 50A) in which half bridge driver ICs in high voltage SOI technology are integrated directly on the DBC substrate of a power module is presented here.
The assembly of the IPM introduced here uses the well established SEMIKRON MiniSKiiP technology. Its success is based primarily on an innovative package without baseplate under the DBC substrate and with spring contacts for all main and auxiliary connections. This leads to an easy assembly construction with high thermal and power cycling capability, as well as vibration ruggedness. Fig. 1 shows an assembly example of such an IPM .The MiniSKiiP IPM consists of the DBC substrate with all power devices, SMD devices, sensors and the driver-ICs, the housing with contact springs for the contact between DBC and PCB and the module lid.
III. 1200V LEVEL SHIFTER CONCEPT
Gate driver ICs, widely accepted, rely on conventional junction isolation with 600V or 1200V blocking voltage to shield the high side from the offset voltage. Though the market has shown considerable interest in these high voltage ICs (HVICs), the junction isolation has still certain fundamental drawbacks. Negative transient voltages at the driver output can trigger internal parasitic structures, leading to latch-up. Also, the operation temperature is typically limited to 150°C because of increasing pn leakage currents.
Figure 1. MiniSKiiP IPM assembly example
As shown in recent papers, gate drive ICs based on a high voltage SOI-CMOS technology   can overcome most of the disadvantages of conventional junction isolation. Because all devices are dielectrically insulated, they provide complete latch-up immunity and the operational temperature range can be considerably extended up to 200°C   - ideal for module integration  . Furthermore an advanced level shifter concept allows negative secondary side offset voltages down to -30V .
Nevertheless, SOI technologies for the 1200V class do not currently exist, because the HV level shifter transistors as well as the vertical dielectric isolation (buried oxide, BOX) between the high side and the handle wafer are not available for this breakdown voltage. To be able to use the specific advantages of the SOI technology for 1200V applications as well, a new level shifter concept was developed by which the available high side offset voltage range is doubled by a series connection of two 600V transistors. The transmission works without further signal processing on the originating intermediate potential. The limited breakdown voltage of the vertical BOX requires the subdivision of the offset voltages onto two physically separated dies. This entails, that all high side functions are integrated in a separate high side IC.
Figure 2. Schematic of 1200V level shifter (single transmission branch)
Fig. 2 shows the principle block circuit diagram of the new 1200V level shifter. The circuit is based on a proven cascode topology for 600V level shifter, which was extended by a second 600V transistor. The operation principle is as follows: If the medium voltage transistor M1 opens both high voltage transistors HV1 und HV2 are turned on. Therefore a crosscurrent flows from the high side supply VB,TOP to low side ground GNDC. The current is limited by the M1 source feedback resistor R1. The voltage drop across R2 (VB,TOPOUT) is the high side raw signal, which is converted back to logic level by the following Schmitt Trigger. The subdivision of the offset voltage across the HV transistors happens dynamically if the TOP-IGBT turns on and is mainly determined by a parasitic capacitive voltage divider. The concentrated devices Cls and Chs summarize all capacitive elements from upper and lower level shifter part which are effective between the intermediate potential and low side reference potential GNDC or high side supply VB,TOP respectively. If Cls and Chs are equal the half offset voltage appears at the intermediate potential. Additionally an active clamping network prevents that the breakdown voltages of the HV transistors are exceeded. The necessary physical separation between upper and lower level shifter part, which are integrated on separate chips, was realized at the gate and the source of HV2, symbolized by the blue dashed line in Fig. 2. The zener diode Z1 limits the gate source voltage of HV2 and provides the necessary coupling between these nodes during switching. The HV diodes D1 and D2 ensure that the gate of HV2 is discharged to VB,TOP when the TOP-IGBT turns off. The source of HV2 will also be discharged due to the coupling to Z1. If the turn off phases of the TOP-IGBTare long enough no intermediate node remains on a higher potential. The handle wafer potential has decisive influence on the breakdown voltage of the used lateral HV transistors. To ensure the effectiveness of the RESURF structure, the handle wafer must be connected to the most negative potential on the chip. This is for the high side IC the source of HV2. The signal transmission to the high side is realized over two parallel level shifter branches, one for the turn on and one for the turn off signals. Therefore the direct connection of the source nodes of both level shifter branches is impossible. The handle wafer of the high side IC is directly connected to the gate of HV2 instead. This solution is feasible because the potential difference between the source and the gate will not exceed some volts. A significant reduction of the breakdown voltage of the HV transistors is not expected.
IV. 1200V HALF BRIDGE DRIVER
Fig. 3 shows the block circuit diagram of the presented 1200V half bridge driver with separation into high side IC and low side IC. The driver provides short pulse suppression (SPS) and hardware interlock. An error management circuit is integrated which processes internal error events (under voltage lockout, UVLO) as well as external error requests applied to the input /ERRIN and over current events detected by the input ITRIP. In case of an error event both channels are turned off and an error signal is given at the error output /ERROUT. An over-current error is triggered if the voltage at sense input ITRIP exceeds an internal generated reference voltage. Inside the IPM the inputs ITRIP and /ERRIN of all half bridge drivers are connected to each other, i.e. all drivers receive the same external error requests. Also the open drain /ERROUT pins are connected. In this manner a wired OR is formed. By the connection of the bidirectional /RESET pins inside the IPM a bus system can be built up between the drivers. In this way an easy initialization and the exchange of status signals are possible. The inputs are compatible to TTL and 3.3V CMOS-logic. The driver outputs provide a peak output current of approximately 1.4A for source and sink at 15V supply voltage and room temperature. The typical signal propagation delay between input and output is about 300ns.
Figure 3. Block circuit diagram of the two-chip 1200V SOI half bridge gate driver
V. MODULE TOPOLOGY AND DBC-LAYOUT
The circuit topology of the IPM is shown in Fig. 4. It contains a three phase inverter consisting of three IGBT half bridges. Each half bridge is driven by a separate 1200V SOI half bridge gate driver. Furthermore a temperature sensor is integrated. Fig. 5 shows the layout of the DBC substrate with all assembled devices. The power semiconductors and the temperature sensor are back side soldered on the DBC and contacted with thick Al bond wires on the front side. The gate driver IC dies are assembled with conductive glue direct on the DBC, which leads to an extreme low thermal resistance  and a high output current capability.
Figure 4. Circuit diagram of the 1200V/50A IPM
Figure 5. DBC-Layout of the 1200V/50A IPM
Figure 6. Two-chip 1200V SOI half bridge gate driver on the DBC
Fig 6 shows the enlarged view of the 1200V half bridge driver integrated on the DBC. The contacts between the IC pads and the DBC copper conducting paths are realized by thin bond wires. The routing of the conducting paths on the DBC is very short and compact, so a low inductivity is reached. The DBC substrate and the mounted devices are protected with silicone gel.
VI. SWITCHING BEHAVIOUR
All switching measurements shown here were performed at inductive load. The switching losses of the 1200V/50A IPM with integrated driver ICs are compared to an equivalent inverter module (1200V/50A IGBT 4 Trench Fieldstop with CAL 4 free wheeling diodes) in the MiniSKiiP package and external hybrid driver (see TABLE I.). Fig. 7 and 8 show the turn on and the turn off behaviour of a BOT-IGBT at 600V DC link voltage.
Table 1. COMPARISON OF THE SWITCHING LOSSES OF 1200V/50A IGBT/FWD CHIPSETS WITH HYBRID (AC) AND INTEGRATED DRIVER (IPM)
Because of the high driver output capability of the integrated drivers the Eoff, Err and Eon (only TOP) values are in the same range like the hybrid driver. Only the Eon of the BOT-IGBT is remarkable higher with integrated driver. This is due to parasitic inductances and resistances in the emitter branch of the BOT-IGBT. This leads to a voltage drop during turn on which reduces the effective gate-emitter-voltage (negative current feedback) and extends the turn on time (see Fig. 7). A low-resistive connection of the BOT driver terminals to the emitters of the BOT-IGBTs directly on the DBC can improve the switching behaviour. This can be realised with an other ground concept, where driver core ground (GNDC) and bottom driver ground VS,BOT are not connected anymore. The voltage drop over the parasitic elements is not eliminated thereby, but occurs in the level shifter of the BOT channel inside the gate driver.
Figure 7. Turn on characteristics (VDC=600V, Iload=50A, Tj=150°C, Eon=7.6mJ)
The much lower measured Eon losses for the TOP-IGBTs confirm that such a ground concept leads to a significant faster switching. (The auxiliary emitter of the TOP-IGBT is directly connected to the VS,TOP terminals of the corresponding high side driver.)
Figure 8. Turn off characteristics (VDC=600V, Iload=50A, Tj=150°C, Eoff=4.5mJ)
Exemplarily for the reached performance Fig. 9 shows double pulse measurement with inductive-resistive load for the TOP-IGBT at maximum DC link voltage of 1200V and at nominal current. This measurement confirms the steady voltage subdivision across the HV transistors of the 1200V level shifter as well as the low-inductive assembly with a maximum overvoltage peak of 1280V at VDC=1200V.
Figure 9. Double pulse measurement of the IPM (TOP-IGBT switched with resistive-inductive load, VDC=1200V Tj=25°C)
VII. POWER INVERTER TEST
The three phase power inverter test of the 1200V IPM was performed under lab conditions. The load was formed by Yconnected inductors (L=170μH). The branch currents were regulated sinusoidal and with 120° phase shift to each other by PWM. Fig. 10 shows as an example the regulated load current (50A/50Hz) of phases U and V for several periods and the output voltage waveform VU of the U phase at 800V DC link voltage and 3kHz PWM frequency.
Figure 10. Three phase power inverter test (Ch1: 30A/div, Ch3: 30A/div; Ch4: 300V/div, VDC=800V, Iout=50A, fout=50Hz, fsw=3kHz)
A new intelligent power module (IPM) for medium and high power in MiniSKiiP package is presented. A robust 1200V SOI half bridge driver with an innovative level shifter concept overcomes the technological limits for the breakdown voltage and is able to drive the IGBTs with high reliability and low losses. With the presented concept the IPM load current range can be extended to approximately 100A. The excellent cooling of the power semiconductors and the drivers allows high operating temperatures and a long lifetime. Therefore the gate driver and the package are also well suited for high temperature operating of SiC devices .
 G. Majumdar, M. Iwasaki, M. Fukunaga, X. Kong, “Compact IPMs in Transfer Mold Packages for Low-Power-Motor Drives”, Proceedings ISPSD, pp. 333-336, 2005.
 H. Kawafuji, T. Nakano, T. Iwagami, K. Kuriaki, M. Honsberg “New 5-35A/1200V Transfer Mold IPM with heat dissipating insulation sheet”, Proceedings PCIM, 2005.
 T. Letavic, E. Arnold, M. Simpson, R. Aquino, H. Bhimnathwala, R. Egloff, A. Emmerik, S. Wong, S. Mukherjee, „High Performance 600V Smart Power Technology Based on Thin Layer Silicon-on-Insulator“, Proceedings ISPSD, pp. 49-52, 1997
 T. Letavic, M. Simpson, E. Arnold, E. Peters, R. Aquino, J. Curcio, S. Herko, S. Mukherjee, „600V Power Conversion System-on-a-Chip Based on Thin Layer Silicon-on-Insulator“, Proceedings ISPSD, pp. 325-328, 1999
 S. Pawel, M. Rossberg, R. Herzer “600V SOI Gate Drive HVIC for Medium Power Applications Operating up to 200°C”, Proceedings ISPSD, pp. 55-58, 2005
 M. Rossberg, R. Herzer, S. Pawel “Latch-up free 600V SOI Gate Driver IC for Medium Power and High Temperature Applications”, Proceedings EPE, 2005
 B. Vogler, M. Rossberg, R. Herzer, L.Reusser, T. Wurm “600V CIBModule with integrated SOI Gate Driver IC for Medium Power Applications”, Proceedings CIPS, pp. 261 – 265, 2008
 M. Rossberg, B. Vogler R. Herzer, L. Reusser “Intelligent Power Module with integrated SOI Gate Driver IC for Medium Power Applications”, Proceedings ISPS, 2008.
 M. Rossberg, B. Vogler R. Herzer “600V SOI Gate Driver IC with Advanced Level Shift Concept for Medium and High Power Applications”, Proceedings EPE, 2007.
 K. El Falahi, B. Allard, D. Tournier, D. Bergogne “Evaluation of commercial SOI driver performances while operated in extreme conditions (150°C - 200°C)”, Proceedings CIPS, pp. 161 – 163, 2010
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