Posted on 02 August 2019

SuperFET® II a Super-Junction MOSFET that Provides Low EMI

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Stable Operation with Excellent Noise Reduction in PFC Applications

Super-Junction MOSFET based on charge balanced technology offer outstanding performance with respect to reduce both on-resistance and parasitic capacitances, which usually are in trade-off. With smaller parasitic capacitances, the super-junction MOSFETs have extremely fast switching characteristics and therefore reduced switching losses.

By Wonsuk Choi and Dongkook Son, Fairchild Korea Semiconductor, HV PCIA PSS Team Bucheon-si Republic of Korea, Application Engineering, E-mail :


Naturally this switching behavior occurs with extremely high dv/dt and di/dt that affect switching performance via parasitic components in devices and printed circuit board. Especially, for super junction MOSFET used in high frequency modern SMPS, it is very difficult to suppress frequency noise and radiated EMI to simultaneously achieve both high switching efficiency and low switching noise. Furthermore, switching noise can lead to some unexpected system or device failures associated with gate oxide breakdown, breakdown dv/dt and latch-up problems in control signal due to severe gate oscillation and high switching dv/dt in various abnormal conditions such as start-up state, overload condition and paralleled operations. To achieve low switching noise, high values of parasitic capacitances or gate resistances are required. Based on recent system trends, improving efficiency is a critical goal; however, using a slow switching device just for reduction of switching noise is not an optimal solution. New generation super-junction MOSFET, SuperFET® II device enables fast switching and low switching noise to achieve high efficiency and low EMI in applications thank to optimized design of SuperFET® II MOSFET.

SuperFET® II MOSFET Technology

It is well known high switching speed of super junction MOSFET is naturally good to reduce the switching losses, but it will give negative effects such as increased EMI, gate oscillation, high peak drainsource voltage on application. One critical control parameter in gatedrive design is the external series gate resistor (Rg). This is dampens down the peak drain-source voltage and prevents gate ringing caused by lead inductance and parasitic capacitances of the power MOSFET. It also slows down the rate of rise of the voltage (dv/dt) and current (di/dt) during the turn-on and turn-off process. But Rg also affects the switching losses in MOSFETs. Controlling these losses is important as devices must achieve the highest efficiency on the target application. Therefore from an application standpoint, selecting the correct value for Rg is very important. SuperFET® II MOSFET employ integrated gate resistor, which is not ESR (equivalent series resistor) but is gate resistor, placed in gate pad, to reduce gate oscillation and control switching dv/dt and di/dt under high current conditions. The value of integrated gate resistance is optimized with gate charge. The gate oscillation of VGS, (Vb) in actual gate of the device is dramatically reduced because voltage drop across gate-source is divided by internal Rg and external Rg. The reverse transfer capacitance, Cgd is one of the major parameters affecting voltage rise and fall times during switching. Cgd provides a negative feedback effect from the drain voltage, and it must be discharged by the gate drive current supplied through Rg. The oscillations are related to several causes such as high switching dv/dt and di/dt, parasitic Cgd and the value of the drain current. The gate charge of SuperFET® II MOSFET is optimized to improve trade-off between switching efficiency and switching noise. Figure 1 shows actual MOSFET dv/dt comparing the fast SJ MOSFETs and SuperFET® II MOSFET during turn-off transient in PFC circuit from 100W to 400W under same driving condition. The linear rise of turn-off dv/dt the fast super junction MOSFET shows that the dv/dt cannot be controlled in the PFC circuit with small gate resistance (3.3Ohm). SuperFET® II MOSFET has reduced increase of turn-off dv/dt compared to the fast super junction MOSFET, but still it is linearly increased under 300W load condition. At full load condition, dv/dt is controlled at 36V/ns which is reduced dv/dt about 30.8%, compared to the fast super junction MOSFET.

Comparisons of measured dv-dt between the fast SJ MOSFETs and SuperFET® II MOSFET

Parasitic Oscillation Mechanism of Super-junction MOSFET

Coss curve of super-junction MOSFET is highly non-linear. These effects will allow an extremely fast dv/dt and di/dt and voltage and current oscillation when super-junction MOSFETs are used as a switching device for PFC or DC/DC converters. Figure 2 shows observed oscillation waveforms in PFC circuit during turn-off transient of super-junction MOSFET. From a general perspective, there are several oscillation circuits which affect the switching behavior of the MOSFET this includes internal and external oscillation circuits. Figure 3 shows a simplified schematic of PFC circuit including both internal parasitics which is given by the parasitic capacitances Cgs, Cgd_int. and Cds and parasitic inductances, Lg1, Ld1 and Ls1 of the Power MOSFET itself and also an external oscillation circuits which is given by the external couple capacitance Cgd_ext. and parasitic inductances, LG, LD and LS of the board layout. Parasitic components are involving switching characteristics more as the switching speed is getting faster. Gate parasitic oscillation occurs in a resonant circuit by internal and external gate-drain capacitance, Cgd_int. and Cgd_ext. and gate inductance, Lg1 and LG, when MOSFET is turned on and off. Oscillation voltage in drain-source of the MOSFET passes through gatedrain capacitance, Cgd due to parasitic inductance, LD when MOSFET switching is getting fast, and particularly when it is turned off, and a resonant circuit with gate inductance Lg1 and LG is formed. As gate resistor is extremely small, oscillation circuit, Q (√L/C/R ) becomes large, and when the resonance condition occurs, a large oscillation voltage is generated between that point and Cgd or LG, Lg1, and parasitic oscillation is caused. Furthermore, the voltage drop across LS and Ls1, which can be represented by equation (1), was cause by negative drain current in turn-off transient. This voltage drop across stray source inductances, LS and Ls1, generates oscillation in gate-source voltage. The parasitic oscillation can cause severe EMI problem, large switching losses, gate-source breakdown, losing gate control and can even lead to MOSFET failures.

Equation 1

Severe oscillation waveforms in PFC circuit using superjunction MOSFET

Simplified schematic of PFC circuit with internal and external parasitics of Power MOSFET

Application Benefits of SuperFET® II MOSFET

Experiment results verify the stable operation of SuperFET® II MOSFET and better EMI results in PFC circuit. The measurement were done in a PFC boost stage at the same input voltage, VIN=110VAC and output power level, Pout=300W during AC on/off test. Figure 4 present waveforms comparing difference in gate oscillations, VGS (yellow line) at start up between the fast super-junction MOSFET and SuperFET® II MOSFET. With fast super-junction MOSFET, high peak gate oscillation, exceeding 45V, is generated. It causes a over voltage latch-up. Finally, it leads to absent of gate signal of power MOSFET as shown in figure 4 (a). A peak Vcc voltage is greatly reduce dup to 16V and latch-up problem is removed with SuperFET® II MOSFET as shown in figure 4 (b). This oscillation effect can be forced if the output power level is increased or the input voltage is decreased at the same output power. This effect can also happen after an AC line drop out, when line voltage is back, the boost stage charge up the bulk capacitor to nominal voltage. During this time, when the MOSFET turns off, the drain current is quite high. The drain current commutates to the output capacitance, Coss of the MOSFET and charges it up to DC bus voltage. The voltage slope is proportional to the load current, and inversely proportional to the value of the output capacitance. The high dv/dt values lead to capacitive displacement currents due to all the parasitic capacitances around. Together with all the layout and parasitic inductance and capacitances an LC oscillation circuit is created only damped by the internal Rg. Under certain conditions e.g. transient at input voltage or shortcut conditions high di/dt and dv/dt occur, and this leads to unusual switching behavior or worst case damaged devices. Nevertheless, with optimized SuperFET® II MOSFET helps to improve efficiency and also stable operation.

Comparisons of waveforms during start-up state in PFC circuit

EMI performance of SuperFET® II MOSFET is verified in 400W ATX power supply. Figure 4 show the measured results of radiated EMI noise between the fast super-junction MOSFET and SuperFET® II MOSFET as a PFC switches. SuperFET® II MOSFET can reduce peak drain-source voltage, peak dv/dt and gate oscillation due to soft switching characteristics of SuperFET® II MOSFET. By using Super- FET® II MOSFET, emission level (dBμV) becomes lower in the fre- quency range from 90MHz to 160MHz. Especially, emission level of SuperFET® II MOSFET is up to 9~10 dBμV lower at 130MHz, compared to the fast super-junction MOSFET as shown in figure 4 (right).

Measured Radiated EMI in ATX Power supply, the fast super junction mosfet and superfet II mosfet


As technology of power MOSFET grew more advanced, super-junction MOSFET lead to smaller chip size but more efficient performances. Extremely fast switching super-junction MOSFET is essential choice for higher efficiency but it is not easy to control than previous generations. New super-junction MOSFET, SuperFET® II MOSFETs that optimize switching performance enable to reduce gate oscillation, EMI noise and improved stable operation in high current operation, such as startup up or over load conditions while maximizing switching performances.



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