Stress induced by thermal cycles causes power electronic systems to have a finite service life. To estimate this service lifetime, accurate information on the thermal profile in the chips under the given operating conditions is required. This paper discusses how the temperature profile can be determined without the need for specially modified modules.
Dr. Uwe Scheuermann, Semikron
When designing power electronic systems, development engineers do not only have the functional aspects in mind, but also factor in the expected service life. To estimate the service life of a system, however, accurate data is needed on the thermal cycles the system has to withstand during operation over the expected operating time.
One-dimensional thermal networks can be used to simulate the thermal behaviour of a power electronics system with a sufficient degree of accuracy. By supplying a characteristic power loss profile into this network, a temperature profile or "mission profile“ can then be calculated. Extracting the number of thermal cycles from the mission profile allows for the evaluation of the expected service lifetime on the basis of an appropriate lifetime model.
While the power losses generated at each operating point can be derived with relative ease from data sheet values, the determination of the correct thermal equivalent circuit proves more difficult. Although many manufacturers of power modules give thermal circuit parameters for their modules in the form of Foster equivalent circuits, this equivalent network apparently cannot account for the userspecific cooling conditions. A Foster network is a series circuit of parallel resistor/capacitor pairs, which results from system theory as a transfer function for stepwise constant power pulses. Since a one-dimensional network of this kind can be calculated analytically, the temperature profile for an arbitrary sequence of power pulses can be easily derived. Nevertheless, it must be emphasized that such transfer functions must not be connected in series.
Therefore, to ensure an appropriate thermal design, the transmission behaviour of the system as a whole has to be emulated by an accurate thermal equivalent model. To do so, the chip temperature has to be determined by way of time-resolved measurements of the complete system.
It is advantageous to use a temperature dependent chip parameter and thus to use the chip itself as a sensor. For an IGBT, the temperature-dependent forward voltage drop for a small sense current is a particularly suitable method, since components commonly used today have an almost linear negative temperature coefficient. For a constant sense current of 100 mA, this results in a typical temperature dependence of ~ –2m V/K. Every component has to be calibrated before the measurement is taken, as the temperature coefficient is subject to a certain production spread.
Once this calibration curve has been established, the chip temperature after load current turn-off can be determined by supplying the sense current through the component and measuring the voltage drop; this procedure is normally referred to as the VCE(T) method. The component, however, first has to reach a state of electrical equilibrium before the temperature measurement can be performed. This time amounts to approx. 50 μs in state-ofthe- art IGBTs. Thus, temperature measurements are possible below 0.1 ms after turn-off. This time resolution is virtually impossible to achieve using external sensors. If, before the load pulse is turned off, the IGBT is in a state of equilibrium, the cooling curve may be measured between 100 μs and several seconds and a correct Foster network can then be derived.
Calibration is done using homogenous heating of the device in a furnace or on a hotplate. During active operation, however, the power chip is not heated homogenously, but displays a lateral temperature gradient (figure 1).
Figure 1. IR camera image of a Trench IGBT (SIGC158T120R3) for 150A in a SEMiX module (SEMiX703GB126D) on a water-cooled heat sink at 9 °C.
This can give rise to temperature differences of 40 °C and more. The question is what geometrical significance the temperature determined using the VCE(T) method actually has.
A study was conducted to investigate this question more closely. For the case described in figure 1, which refers to an IGBT loaded with a constant power loss of 273 W, a VCE(T) measurement resulted in a virtual junction temperature of 108.5 °C. A three-dimensional model of the module set-up including heat sink then was generated. By adapting the effective thickness of the thermal paste layer and the heat transfer coefficient between heat sink and cooling water, a good approximation of the thermal behaviour of the real system was achieved.
Figure 2. Comparison of the IR camera reading along the chip diagonal with corresponding temperature. An overview of all results is also shown here
The impedance characteristic calculated from the simulation by current-related averaging is almost identical to the impedance curve measured using the VCE(T) method
Figure 2 shows a comparison of the measured and simulated chip temperature along a diagonal section through the chip center.
What was taken into account in the simulation was the measuring current distribution. Owing to the negative temperature coefficient of the measuring current, a higher current density is established in the warmer chip regions. The current-related average temperature reading was 108.9 °C. An area-related average of the temperature distribution obtained from the simulation resulted in a temperature of 108.1 °C. At 106.6 °C, the area-related reading taken by the IR camera was slightly lower due to the shading caused by the wire bonds.
These results show that the VCE(T) method delivers a virtual junction temperature which corresponds with a current- related average of the temperature distribution in the chip. As shown in figure 3, a correct depiction of the transient thermal impedance is also delivered. The fact that these values are very much concurrent with the temperature value obtained by area-related averaging shows that the VCE(T) method is an ideal procedure for comparing measurement and simulation results.