Confirm zero-voltage switching during all operating conditions
The half-bridge or ‘totem-pole’ configuration is one of the most common switch circuit topologies used in power electronics today. It is used in various applications such as synchronous buck converters, resonant converters, electronic ballasts, induction heating and motion control, and offers such benefits as four-quadrant switching, zero-voltage switching (ZVS), zero-current switching (ZCS), high-frequency operation, low EMI and high efficiency.
By Tom Ribarich, International Rectifier, Director, Lighting Systems and Applications
As simple as this switch configuration appears, it is actually ‘deceptively’ simple. Much care should be taken during the design of the half-bridge and drive circuitry to avoid many hidden pitfalls. This article provides a short review of the half-bridge and how it works, illustrates proper gate drive circuits and layout techniques, and describes various circuit pitfalls and how to avoid them.
The Half-Bridge Circuit
The half-bridge circuit consists of an upper and lower switch (typically MOSFETs) connected in a cascode arrangement (Figure 1). This 5- terminal circuit includes a DC bus voltage input (1), a mid-point between the two switches (2), a ground return (3), a low-side gate drive input (4) and a high-side gate drive input (5). The input, output and Miller capacitances, as well as the anti-parallel diodes, of each switch are also included in the circuit and are important for understanding the half-bridge functionality.
The two switches are turned on and off complementary to each other (and with a non-overlapping dead-time) by applying the correct voltage waveforms at each of the gate drive inputs. The result is a square-wave voltage at the mid-point that switches between the DC bus voltage and ground (Figure 2). With a series R-C-L load connected between the mid-point and ground, an AC current is produced in the load circuit as the square-wave at the mid-point oscillates up and down. A portion of this AC current flows in each of the half-bridge switches, depending on which switch is on or off. The voltage and current waveforms can be divided up into the following four time zones.
Zone I: The upper switch turns on and the mid-point is connected to the DC bus voltage. Current flows from the (+) side of the DC bus capacitor, through the upper switch, through the R-C-L load, and back to the (-) ground return path. The current ramps up to a positive peak level during the on-time of the upper switch.
Zone II: The upper switch turns off and both switches remain off during this short dead-time. The load current continues to flow out of the mid-point node. Half of the load current flows out of the top of the lower switch output capacitance (CDS2), and the other half flows out of the bottom of the upper switch output capacitance (CDS1). This causes the mid-point voltage to slew down to ground at a given dv/dt rate determined by the total capacitance at the mid-point and the instantaneous load current. The mid-point voltage reaches ground and continues to go negative until it gets limited by the internal antiparallel diode (D2) of the lower MOSFET (S2). This diode, also known as the ‘free-wheeling’ diode, allows the R-C-L current to flow in the negative direction while the switches are off.
Zone III: The dead-time ends and the lower switch turns on. Because the mid-point voltage is at ground, zero-voltage switching (ZVS) occurs when the lower switch turns on. Current continues to flow through the channel of lower MOSFET (instead of the diode due to the lower resistance of the channel) and through the R-C-L circuit. The current crosses zero and continues to ramp down to a negative peak level during the on-time of the lower switch. No current flows through the DC bus capacitor during this time.
Zone IV: The lower switch turns off and both switches remain off again during this deadtime. The load current continues to flow into the mid-point node and is equally split between both output capacitances (CDS1 and CDS2). The mid-point voltage slews up at a dv/dt rate determined by the total midpoint capacitance and the instantaneous load current. The mid-point voltage gets limited by the DC bus voltage plus the diode drop of the internal anti-parallel diode (D1) of the upper MOSFET (S1). The current continues to flow through this diode until the upper switch is turned on again at the start of Zone I. Because the mid-point voltage is at the DC bus voltage at the end of Zone IV, zero-voltage switching (ZVS) is achieved when the upper switch is turned on again at the beginning of Zone I.
In order to maintain ZVS across both switches, it is necessary that the mid-point voltage leads the load current during each switching cycle. This ensures that the mid-point voltage properly slews to the opposite rail during each dead-time. If the mid-point voltage is in-phase or lags the load current, then mid-point voltage will not slew to the opposite rail during the dead-time and “hardswitching” will occur (Figure 3). A large spike of current will occur at the turn-on of each switch as the mid-point capacitance is instantly charged or discharged. This gives high switching losses and can cause the switches to thermally destruct.
When ZVS is achieved in this resonant application, switching losses and EMI are significantly reduced. The reduced switching losses then allows for higher switching speeds for reducing the size of the magnetics. The four-quadrant operation of the halfbridge also allows for the load current to flow in the positive and negative directions without interruption.
Gate Drive Circuits
The half-bridge requires a low-side gate drive circuit (referenced to ground) for turning the lower MOSFET on and off, and requires a “floating” high-side driver (referenced to the mid-point) for turning the upper MOSFET on and off (Figure 4). The type of gate drive circuit used depends on the input and Miller capacitances of the MOSFET, the switching frequency, and the half-bridge current amplitude. If the current is low (<500mA) and the switching frequency is low (<100kHz), then a standard 600V, high and low-side gate driver IC (such as the IRS2101) and series gate resistors (RG1, RG2) are usually sufficient. If the half-bridge current is higher (1A), then it is desirable to turn off each MOSFET quickly to minimize switching losses at turn-off. Usually the higher half-bridge currents require larger MOSFETs with larger parasitic capacitances. In this case, an anti-parallel diode (DG1) is placed in parallel to the gate resistor to discharge the gate capacitance quickly during turn-off. However, care must be taken for the current that flows through the Miller capacitance and back into the gate driver IC when the mid-point voltage slews to the opposite rail during each dead-time. An additional smaller resistor (RG3) should be placed in series with the anti-parallel diode to limit high Miller currents from causing latch-up inside the gate driver IC. Also, the RDSon of the sink current gate driver switch becomes critical and can cause a voltage offset to occur due to the Miller current that can momentarily turn the MOSFET back on. An external PNP transistor (Figure 4) can be used instead of a diode to increase the sink current capability of the gate drive circuit, or, a gate drive IC with larger I/O current capability can be used (such as IRS21856). At higher frequencies (<500kHz), the switching losses at turn-off increase, as well as the internal losses of the gate drive switches and level-shifting losses when turning the high-side MOSFET on and off. A gate driver IC that is specifically designed for higher frequencies and higher gate drive currents is typically required (such as IRS2795).
The pcb layout is a critical piece of the overall design and needs to be properly designed for good robustness. A poor layout can cause reliability issues that go “undetected” until the product reaches high volume manufacturing or is working in the field. The half-bridge midpoint is a major source of noise in the circuit as it oscillates between ground and the DC bus voltage at a given frequency. This node should therefore be kept as far away as possible from any critical low-voltage control or sensing circuits to avoid noise coupling due to parasitic pcb capacitances. The IC and small-signal component grounds should all be connected together and then connected to the power ground trace at a single point only (do not run power ground through the small-signal ground!). Multiple connections from the ground pads of the small-signal components to the power ground add “invisible” parasitic inductors into the control circuit that cause unwanted noise spikes each time high currents flow in the power ground. These spikes can cause faulty switching, jittering, or electrical over-stress across components or at the pins of ICs. For the gate drive, the half-bridge MOSFETs should be placed as close as possible to the gate drive circuits to reduce any possible parasitic inductance. Each time the MOSFETs are turned on or off, this network of parasitic inductors and MOSFET capacitances can cause ringing at the gates that can swing below ground or above VCC. This can then cause high currents to flow in or out of the gate drive pins of the IC and result in destruction due to latch-up. For higher current applications, it is good practice to add additional zener diodes from the gate to the source of each switch. This will help limit the voltage from swinging too far below ground or above VCC. A typical half-bridge layout using SMT components for the schematic in Figure 4 is shown in Figure 5 to help illustrate good pcb techniques.
The half-bridge circuit is an elegant solution for many switched-mode applications that offers many benefits. But these benefits are realizable only when the half-bridge circuit, the gate drive circuit, and layout, are all properly designed. The half-bridge mid-point voltage and current waveforms should be checked carefully to confirm that ZVS is maintained during all operating conditions. Partial or hard-switching can give high switching losses and cause the switches to overheat and thermally destruct. The gate drive circuit should be properly designed so that it is suitable for the size of the MOSFET being driven, the amplitude of the halfbridge current, and the operating frequency. Finally, much care should be taken during the design of the layout to avoid long gate drive loops or poor grounding that can cause IC latch-up, EMI, or faulty switching.