Posted on 01 September 2019

The Help of Thermal and Mechanical Analysis

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Modules to handle higher power levels

Power electronics applications continue to demand cost-effective power modules with ever-increasing efficiency and performance. Semikron is meeting this need by introducing the SEMITOP 4 “baseplateless” module.

By Fabio Brucchi, Semikron Italia


This device retains the SEMITOP family’s “one screw mounting” technique, while handling up to 22 kW motor power from a 58.5×53mm footprint (590 W/cm3).Power electronic applications are continuously demanding cost-effective power modules with increased efficiency and performances. Current density in power modules has shown a continuous linear growth throughout the last decade. For example, 600V IGBT dice increased from 120A/cm2 in 1996 to over 190A/cm2 in 2005. In the same way, 600V fast CAL diodes were developed from 160A/cm2 in 1992 to 230A/cm2 in 2004.

This continuous need is met by introducing the “baseplateless” one screw mounting SEMITOP®4 module. The minimum specification to make this module attractive to the market (keeping the same reliability level as the smaller SEMITOP modules) was:

Power rating: twice the power rating of SEMITOP 3
Power density: 30% higher than SEMITOP 3
Thermal resistance (junction-to-sink): 20% less than SEMITOP 3
Topologies: six-pack (IGBTs and MOSFETs) and Converter Inverter Brake

The trend of increased power density of power electronics applications coupled with the need for cost containment of power electronic applications has brought about reductions in electrical and safety margins.

Figure 1 shows the well-known dependency of the number of cycles with temperature swings (LESIT curves) for a power electronics module, and emphasises the importance of a correct thermal design.

LESIT Curves for reliability of power modules

Nf = Number of power cycles
kB = Boltzmann constant =1.38·10-23 J/K
Ea = Activation energy = 9.891·10-20 J
A = constant = 302500 K-a
α = constant = -5.039
Tm = medium junction temperature

For this reason, in order to achieve a successful and reliable power module, many thermal phenomena (such as thermal interference, temperature contour distortion and border effect) which have often been considered to be of secondary importance (or sometimes even neglected) have been considered now. Due to the fact, that the housing also functions as a pressure system, an accurate mechanical dimensioning study has also been performed.

Mechanical simulations and design

To meet increased quality requirements and to avoid critical aspects in terms of the substrate’s mechanical stress, a finite element mechanical analysis has been performed on different shapes, structures and housing materials.

This analysis reduced the expensive tests usually necessary to verify the trial housings made by milling machines and reduced the testing of plastic mould tooling.

Moreover, these simulations also reduced the time for prototyping and the number of revisions of the final tooling.

Figure 2 shows an example of such a comparison. The high level of mechanical deformation of a SEMITOP 4 prototype housing screwed onto a heat-sink and made in standard polymer (ABS, Figure 2a) is compared to the final design made in GF reinforced polyimide (Stanyl, Figure 2b). It is easy to see that in the wrong design the applied torque to the centre screw leads to excessive deformation of the housing (over 1.3mm), while in the final design the maximum mechanical deformation is about 320μm. Furthermore, in terms of mechanical pressure on the substrate, applying the nominal torque to the centre screw, the mechanical stress (according to Von Mises) was reduced from 500MPa (initial design) to less than 200Mpa (final design), which is broadly within the Weibull Modulus statistical limit of the ceramic bending strength failure (three point method).

Mechanical displacement of SEMITOP 4 with standard polymer

Mechanical displacement of SEMITOP 4 with GF-reinforced polyimide

Thermal Simulations and Design

To meet increasing power density requirements, more and larger dice populate the same area in today’s modules. This makes it necessary to dissipate into the heat-sink the same (or even increased) power levels from ever-smaller areas.

This means that thermal interference, distortion of temperature contours and the interaction of all these phenomena have to be taken into consideration. This leads to a different approach to power electronics module design.

So, the typical coefficients used for Rth(j-s) calculation have to be revisited as a function of the power module and as a function of the specific customer application.

With the introduction of user-friendly finite element analysis software and the increasing calculation power of PCs, finite element models (FEMs) can be generated very quickly. Starting from 3D-files or 2D-CAD files, complete and detailed substrate layout analysis can be produced in a few hours. This allows a time-effective generation of a great number of FEMs and the handling of huge amounts of data (which has been impossible up to now with standard FE software and PCs, which could take several days to produce a complete FEM).

It has been possible to verify the Rth(j-s) distribution for each customised layout and to identify every possible thermal critical aspect. The potential critical points are then discussed with the final customer to evaluate the effective critical response in the real application.

Table 1 compares the measured maximum IGBT and FWD Rth(j-s) values on trial housings vs. FEA results.

Comparison between measured Rth(j-s) and simulated Rth(j-s) for each IGBT and FWD (SK100GD126T).

Measurements are based on the international IEC747-8/2.18 standard. This is an indirect method which uses the Vce(sat) to monitor the Tj. This value is a “sort of average” temperature of the die’s junction temperature. For this measurement to be consistent with FEA, we used a weighted average chip temperature to get the Tj value and the heatsink temperature Ts in the exact position where the temperature probe was placed during measurement.

It is important to specify this because the temperature across a silicon die (particularly in paralleled dice) can vary by several degrees (for example, in Figure 3a Tj varies from 114°C to 96°C on the same die). The incorrect choice of measurement points can falsify the simulation result.

Rth(j-s) measurement at PD=121.6W. Junction temperature contour (TJ(max)=111.47°C).

Rth(j-s) measurement at PD=121.6W.

When running at high power dissipation, each die receives from the adjacent one a high thermal interference level. Furthermore, temperature contour distortion and border effect lead to an increased Rth(j-s) level.

For example, Figure 4 shows this difference, using different power dissipation levels than those used for the Rth(j-s) measurement and with lower die-to-die distances.

Simulation of SK100GD126T module running in application with specification of each Rth(j-s).

Figure 4 also shows the temperature sensor, which is positioned at the upper right corner of the power hybrid. With the FEA it is possible to check the real temperature “seen” by the temperature sensor (96°C, which is about 17°C lower than the hottest point in the module) and to compare it with the switch temperature to give a more accurate figure for Tj, instead of having the usual generic indication of the power hybrid’s temperature.

Using this new design approach it has been possible to verify the Rth(j-s) variations as a function of die-to-die distance, die shape and area and die-to-border distance for “baseplateless” modules.

In particular, Figure 5 shows Rth(j-s) as a function of die distance for two paralleled dice (keeping a minimum die-to-border distance of 5mm in order to avoid border or temperature contour distortion effects). The consistency of these graphs has been cross-checked by comparing measurements on SEMITOP®3 and SEMITOP®2 modules following the IEC 747-8/2.18 international standard for Rth and Zth measurement.

Rth(j-s) as a function of dice distance for two paralleled dice and different die size

In addition, it was found that border effects and even die shape are not negligible when die-to-die distance is less than 3-4mm in a “baseplateless” module. In fact, we found that when two or more dice are paralleled, Rth(j-s) is strongly influenced by the length of the adjacent die’s parallel side. For example, three rectangular dice can be paralleled with adjacent short sides or adjacent long sides. In the second case, the Rth(j-s) value was over 17% greater than when we paralleled the three dice with short adjacent sides. This is mainly due to the combination of deformation of temperature contours and thermal interference phenomenon (the simulation was performed trying to avoid border effect, then using a die to border distance greater than 5mm).

It is then easy to see that Rth(j-s) in paralleled rectangular dice having adjacent shorter sides is smaller than Rth(j-s) in paralleled squared dice at the same measurement conditions and at the same total switch silicon effective area.

In our research, we found that Rth(j-s) can shift from its typical value by over 40% in a power module with high die density, because of thermal interference and the border effect.

SEMITOP 4 – The Technology

To achieve the design aims, and keeping in mind the new FEA simulation, a new substrate has been used. This has different thicknesses of insulator and copper topside/backside, and improved thermal performance, compared to the smaller SEMITOPs. The substrate chosen has a thickness of 0.38mm Aluminium Oxide (Al2O3) with Curamik pre-bent technology. It is especially suitable for modules without a “baseplate” and allows an even thermal paste distribution while still only using one central mounting screw.

The thermal paste thickness does not need to be increased, compared to SEMITOP 3.

The module outline dimensions are: W=60mm, L=55mm, H=12mm. It is fully compatible with SEMITOP 1, 2, and 3; i.e. it is possible to use it in combination with the existing SEMITOP 1, 2, and 3 on the same circuit board and on the same heat-sink.

The module is available in three-phase IGBT (and MOSFET) inverter (from 65A/1200V up to 155A/600V at TJ 25°C) and in Converter Inverter Brake (from 45A/1200V up to 90A/600V at TJ 25°C) topologies.

The following are the results achieved with this technology: Topologies: Six-pack (IGBTs and MOSFETs).

Converter Inverter Brake

Power rating compared to SEMITOP 3:
3.6 times more for the 600V IGBT inverter
3.1 times more for the 1200V IGBT inverter
3.8 times more for the 600V IGBT CIB
3.5 times more for the 1200V IGBT CIB

Power density compared to SEMITOP3:
38% higher than 600V three-phase IGBT inverter
47% higher than 1200V three-phase IGBT inverter

Thermal resistance (junction-to-sink)

Thermal Resistance Measurement and Simulation

A SK100GD126T inverter in SEMITOP 4 (1200V/75A at Ts=80°C) has a typical thermal resistance of 0.39K/W. The same silicon dice mounted into SEMITOP 3 show a typical Rth(j-s) of 0.49K/W. This is a reduction of about 20%.

SEMITOP 4 brings more power to the existing SEMITOP range of modules (without “baseplate”, one centre-screw mounting). The higher power range allows for applications such as drives and power supplies up to 40kVA inverter power.


A different substrate with improved thermal performance has been used. The maximum power rating of IGBT inverter in SEMITOP 4 is over three times greater than existing SEMITOP 3 inverters. These modules have been designed using mechanical and thermal finite element simulation software to meet any critical mechanical and thermal factors, even in the worst environments. With the help of this software, a different approach to power electronics design has been implemented.



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