Posted on 29 June 2019

The Next Generation Chipset Technologies for Higher Operating Temperatures

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This article presents a newly developed 1700V IGBT and diode chip set generation with optimized performances for 175°C junction temperature operation.

By B. Aydin, C. Corvasce, ABB Switzerland Ltd, Semiconductors


Over the past few years, most of the efforts in power semiconductors development have been targeting the increase of the power density for a given application. Such a performance target can be achieved by reducing the losses, increasing the safe operating area and maximizing the allowable junction temperature during operation. A higher allowable junction temperature of the semiconductor offers better conduction of the generated heat and hence, an increase in the power density for a given device area. The design of power electronic devices operating at ever increasing temperatures brings several challenges: demonstrate the switching capability by keeping the maximum ratings at the maximum specified junction temperature (Tjmax) and also prove stable temperature-dependent performances and high reliability levels at Tjmax [1]. Here we present the 2nd generation of the 1700V SPT+ IGBT, able to be operated up to a maximum junction temperature of 175°C. The new IGBT design combines the advantages of an optimum profiling of the enhancement layer with a novel termination technology, offering outstanding performances for low to medium inductance applications as required in automotive, industrial and regenerative power source fields. The performance chart in inverter mode of a module mounting three IGBTs and three anti-parallel diodes which can typically operate in a medium inductance application has been simulated and is shown in Fig. 1. The results clearly illustrate the advantages given from the new chip set technology platform when compared with the previous SPT+ chip set, which was specified for Tjmax=150°C and optimized for high inductance applications. The reduction of the conduction losses achieved in the 2nd generation of the SPT+ technology offers an increase of 8% (green line) in the inverter output current over the frequency range from 250Hz to 1000Hz in a typical water-cooled application. When combined with the 25°C higher temperature capability, the improvement increases up to 20%, as shown in the red line.

Simulation of the inverter output current vs. switching frequency 175°C operation capability.

2nd Generation SPT+ IGBT Technology

The SPT+ IGBT planar technology successfully introduced in 2005, is avaible in different voltage classes ranging from 1.2kV to 6.5kV [2]. The key advantage of the SPT+ technology is the reduction of the conduction losses when compared with the original planar IGBT cell while maintaining the same controllable switching behavior of the SPT (Soft Punch Through) vertical design. This is achieved by introducing an optimized n-type enhancement layer surrounding the Pwell in the IGBT MOS cell, as shown in the cross section in Fig. 2a.The enhancement layer improves the carrier concentration on the cathode side of the IGBT, thus lowering the on-state voltage drop without significantly increasing the turn-off losses. However the n-type enhancement layer has the inherent problem of reducing the blocking capability of the device and possibly increasing the cell sensitivity to dynamic avalanche failures. Hence, the shape of the enhancement layer doping profile must be carefully optimized in order to maximize the enhancement feature and minimize the loss of blocking and avalanche performance. This can be achieved by narrowing the doping profile and increasing the peak concentration as sketched in Fig. 2b. As a result, the high electric field area is reduced with minimum impact on the blocking capability and the plasma concentration at the cathode side is further enhanced with an effective reduction of the conduction losses.

The SPT+ planar cell (a) and of the optimized enhancement profile used in the 2nd generation 1700V SPT+ IGBT (b).

Thanks to the beneficial effect on the blocking capability of the optimized enhancement profile, a thinner n-base design can be used for the 2nd generation SPT+ IGBT with a consequent further reduction of the on-state losses. A reduction of more than 450mV in the conduction losses is achieved using the new technology when compared to the SPT+ platform which, targeting high inductance applications, was designed with thicker silicon.

To guarantee reliable operation at high temperatures, a new termination design based on the biased ring concept has been developed. The termination consists of a number of diffused rings contacted by metal islands and interconnected by a semi-insulating layer, as shown in the schematic cross section in Fig. 3a. This termination design has been proven to be immune to inter-ring distance variations and interface states while offering a narrower leakage current distribution when compared to the previous termination design, which was based on the junction termination extension concept. Thanks to this design and process, the leakage current at Tj=125°C and VCE=1700V has been dramatically dropped to a typical value of 120µA, a reduction by a factor of 4 when compared to the values achieved from chips with a non-optimized passivation process, as shown in Fig. 3b. This low leakage current level has been proven to enable stable operation at Tjmax=175°C and for 2500V – 3300V at Tjmax=150°C.

New termination design (a) and the probability plot of the leakage current measured at VCE=1700V and Tj=125°C (b).

Field Shielded Anode (FSA) Diode Technology

The conventional SPT+ diode uses locally incorporated deep levels by H+ irradiation for local lifetime control in order to tailor the plasma distribution and guarantee stable operation at Tjmax=150°C. In this design, shown in Fig. 4a, the electric field evolving during reverse blocking penetrates the zone of radiation defects already at very low reverse voltages. This generates a leakage current which does not allow stable blocking operation of the chip at Tjmax=175°C. The newly developed Field Shielded Anode (FSA) [3] is characterized by a modified doping profile. The depth of the anode is maintained by introducing a deep profile with a reduced concentration and resembling a low p-doped buffer, preventing the electric field from reaching the zone of radiation defects during blocking. In addition, a shallow highly doped p-layer ensures good contact and good anode injection in the highcurrent region to enable a good surge current capability.

The conventional SPT+ diode and the FSA diode (a) showing the probability plot of leakage measured at VR=1700V and Tj=125°C (b).

The radiation defects position and concentration are then tuned to tailor the plasma distribution to match the conduction and dynamic properties of the SPT+ diode. This FSA design has the inherent advantage of separating the radiation defects from the space charge region resulting in a significantly reduced high temperature leakage current. Figure 4b shows the comparison between the leakage current distributions of the FSA diode chip when compared to the conventional SPT+ platform. The reduction by a factor of 3 in the leakage current measured at Tj=125°C and VR=1700V allows the FSA diode to be operated at Tjmax=175°C.

Because the FSA diode is realized by using a single mask step, the vertical anode profile is also introduced in the horizontal direction. A careful optimization of the lateral design is therefore needed to reach the very high robustness of the conventional diode.

1700V Chip Set Performance

Extensive measurements have been carried out to verify the performance of the new 1700V chip setup to the maximum junction temperature of 175°C. A stray inductance value of 200nH per IGBT chip rated 150A, and 100nH per diode chip rated 300A have been used.

Static Characteristics

In Fig. 5a, the on-state curves of the 2nd generation 1700V SPT+IGBT can be seen. The typical on-state voltage drop (VCE,on) at nominal current and Tj=125°C is 2.45V. The IGBT shows a strong positive temperature coefficient of VCE,on, starting already at low currents up to Tj=175°C, which enables good current sharing capability in applications requiring multiple chip paralleling.

On-state characteristics as a function of the maximum junction temperature: (a) IGBT, (b) FSA diode.

The typical forward voltage of the 1700V FSA diode measured at Tj =125°C is 2.15 V, as shown Fig. 5b. The diode also exhibits a positive temperature coefficient starting at 200A well below the nominal current, which is the result of an optimized local carrier lifetime profile. The temperature coefficient turns tnegative from 150°C with a VF decrease of less than 1mV/K. In the case of a weak negative temperature coefficient, the thermal coupling between the diode and IGBT chips in the module is still sufficient to avoid thermal runaway of the diode with the lowest forward voltage.

IGBT Switching Characteristics

In Fig 6, the switching waveforms of the new 1700V IGBT are shown as measured under nominal conditions i.e. at 150A and 900V at Tj=175°C. In the turn-off test (Fig. 6a), the IGBT was switched off using an RG,off of 9.4Ohm with a stray inductance of 200nH which results in a voltage rise of 4260V/μs. The optimized N-base region combined with the SPT buffer allows the collector current to decay smoothly, ensuring soft turn-off behavior without any disturbing voltage peaks or oscillations.

IGBT switching waveforms at Tj=175°C: (a) turn off, (b) turn on.

Figure 6b shows the turn-on waveforms under nominal conditions at Tj=175°C. The low input capacitance of the planar SPT+ cell allows a fast drop of the IGBT voltage during the turn-on transient. This, combined with the low loss FSA diode brings the turn-on switching losses down to a typical value of 68mJ. The reverse recovery waveform of the FSA diode under nominal conditions at Tj=175°C is mirrored in the turn-on current waveform. By carefully designing the anode profile and the local lifetime control peak, a short, but still smoothly decaying current tail was achieved resulting in total recovery losses of 113mJ.

In order to evaluate the SOA performance of the 2nd generation 1700V SPT+ IGBT technology, the chips have been subjected to a wide range of switching tests under extreme conditions in terms of current, voltage and stray inductances. Figure 7a shows the IGBT chip turn-off capability of two parallel chips measured at Tj=175°C without an active clamp. The chip withstands a strong dynamic avalanche regime turning off a current higher than four times the nominal value without any oscillation. The reverse recovery safe operating area (SOA) of the new FSA technology was extensively investigated over the whole temperature range using high DC-link voltage and high stray inductance (VDC=1400 V, LS=800nH). The current was stepped up to 2 times the nominal value and, after a successful pass, the reverse recovery di/dt was increased by lowering the gate-resistor value (RG, on) and by increasing the gate voltage of the switching IGBT until the diode failed. In Fig. 7b, the last pass reverse recovery waveforms of the 1700V FSA diode can be seen. The diode manages to withstand a reverse recovery current speed of 1.6kA/µs resulting in a peak power of 550kW. This high recovery ruggedness was achieved thanks to the optimization of the anode design in con- junction with the resistive extension of the active junction explained above.

RBSOA capability of new 1700V IGBT chip (a) and FSA diode (b) at Tj=175°C.

IGBT Short Circuit and Diode Reverse Recovery Softness

The excellent short circuit capability of the new 1700V SPT+IGBT is shown in Fig. 8a where the short circuit waveforms at Tj=175°C and a DC-link voltage of 1300V can be seen. After the test thermal runaway occured for pulse times up to 17μs with a short circuit current of 440A and a total dissipated energy of 9.8J. The SPT buffer and anode design used in the SPT+ IGBT have been optimized in order to obtain a high short-circuit capability, even at gate voltages exceeding the standard gate drive voltage of 15V and over the whole junction temperature range from - 40°C to 175°C.

IGBT Short Circuit at Tj=175°C, (a) and Diode Reverse Recovery Softness at Tj=25°C (b).

In Fig 8b the reverse recovery softness test performed at 1/10th of the nominal rated current at a DC-link voltage of 1300V and using double the nominal stray inductance (LS=200nH) is shown. It confirms the soft recovery behavior showing only small oscillations and a peak overshoot voltage of 1360V.



1) Schlapbach U. et al., “1200V IGBTs operating at 200°C? An investigation on the potentials and the design constraints,” Proc. ISPSD’07, Jeju Island, 2007.
2) Rahimo M. et al., “SPT+, the Next Generation of LowLoss HV-IGBTs,” Proc. PCIM’05, Nürnberg, Germany, 2005.
3) Matthias S. et al., “Field Shielded Anode (FSA) Concept Enabling Higher Temperature Operation of Fast Recovery Diodes,” Proc. ISPSD’11, San Diego, USA, 2011.



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