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Posted on 08 October 2019

Thermal Efficiency of Chipscale Packaging for eGaN® FETs

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Semiconductor packaging has been saddled with four key complaints since the advent of the solid state transistor; (1) packages have too much resistance, (2) they have too much inductance, (3) they take up too much space, and (4) they have poor thermal properties that limit heat extraction.

By David Reusch, Johan Strydom, and Alex Lidow, Efficient Power Conversion Corporation

In 2010 enhancement mode gallium nitride power transistors were introduced without a surrounding plastic package. The unique characteristics of the lateral GaN-on-silicon transistors enable the active devices to be protected from the normal environmental abuses without a cumbersome molded plastic package. These chip-scale packages, with a Land Grid Array (LGA) format, eliminate the parasitic inductance and resistance of the semiconductor package as well as the space occupied a conventional package. In this paper we explore the fourth key complaint, thermal performance of the chip-scale package, and we compare this performance with the state-of-the-art power MOSFET packaging available today.

Thermal models

To set the stage for the thermal analysis, let us first look at the physical construction of the chip-scale package. In figure 1 is the EPC2021 eGaN FET [1].

Enhancement mode gallium nitride power transistor (EPC2021 [1]) in a chip-scale package. Shown are the solder bars that are mounted face down on a PCB.

The solder bars make connection between the PCB and the gate, source and drain of the transistor. The top row of bars is separated from the bottom row in order to make ample room for vias on the PCB that can pull heat from the center of the transistor to the back of the PCB.

The solder bars mate with traces on a printed circuit board, and the final assembly might look like the buck converter in figure 2.

48 VIN – 12 VOUT buck converter with enhancement mode gallium nitride transistors mounted face-down on PCB

In figure 3 is shown a cross sectional diagram of a device mounted on the PCB.

Components of thermal resistance for the device in figure 1

The arrows show the various paths for heat to be removed from the active junction of the transistor and can be defined as follows:

  • RƟJC (Thermal resistance from junction to case): This is the thermal resistance from the active part of the eGaN FET to the top of the silicon substrate, including the sidewalls.
  • RƟCA (Thermal resistance from the case to ambient). This is the thermal resistance from the top of the silicon substrate, including the sidewalls, to ambient.
  • RƟJB (Thermal Resistance from junction to board). This is the thermal resistance from the active part of the eGaN FET to the PCB. For this path the heat must transfer through the solder bars to the copper traces in the board.
  • RƟBA (Thermal resistance from board to ambient). This is the thermal resistance created by the PCB itself from the solder connection to the eGaN FET to ambient.

It is straightforward to add a heatsink to this device as has been described in the literature [3]. With a heatsink attached to the silicon substrate two additional resistances that replace RƟCA, must be added to the model, RƟTIM – the thermal resistance of the thermal interface material separating the silicon substrate from the heatsink, and RƟHA – the thermal resistance of the heatsink to ambient. For the purpose of this analysis we will only consider devices without a heatsink.

Package comparisons

The thermal efficiency of a package can be determined by comparing the two parameters that are uniquely determined by the package, RƟJC and RƟJB, normalized to the package area. In table 1 is a compilation of this data for several popular surface mount MOSFET packages as well as two popular eGaN FETs.

Comparison of package area and thermal resistance components RƟJC and RƟJB

In figure 4 is a plot of the junction-to-PCB resistance for each of these packages.

RƟJB (Junction to PCB Thermal Resistance) for several package styles

Red dots represent the MOSFET packages, and blue dots represent the eGaN FETs. All of the packages sampled fall on a single trend line indicating that performance for this element of thermal resistance is determined primarily by package size, and not technology. In contrast, in figure 5 is plotted the thermal resistance from junction to case (RƟJC).

RƟJC (Junction to Case Thermal Resistance) for several package styles. eGaN FETs (represented by blue squares) have superior thermal resistance

The CanPAK and double-sided cooling SO8 packages are far less efficient at getting the heat out of the top of the package than either the Blade package or the eGaN FETs. The eGaN FETs, however, are over 30% lower than the even the Blade when normalized to the same area.

The conclusion that can be drawn is eGaN FETs in chip-scale packaging can achieve higher power density than any power MOSFET in a commercially available package today.

High Power Density DC-DC Conversion

It has been previously demonstrated that the chip-scale packaging of eGaN FETs have extraordinarily small parasitic inductance and virtually zero parasitic resistance [11]. Add to this the almost ten times faster switching speed and the superior thermal efficiency, and large improvements can be realized in power density.

To illustrate this performance gap two buck converters were constructed with virtually identical layout as shown in figure 6.

Buck converter thermal resistance comparison

The board on the left has eGaN FETs, and the board on the right has MOSFETs in 3mm x 3mm S3O8s with similar voltage and on-resistance ratings. Because GaN transistors require a smaller die size to achieve the same on resistance as that of a silicon power MOSFET, and because they require no additional packaging, the resulting transistor footprint on the PCB is 38% smaller in the eGaN FET-based buck converter.

With both converters powered up at 1 MHz with 12 VIN and 1.2 VOUT, the performance difference can be measured both thermally and electrically. In figure 6 the thermal image shows that the peak temperature of the eGaN FET-based buck converter is 17oC (13%) lower than the MOSFET-based converter. This temperature discrepancy is plotted in figure 7 against output current with both zero airflow and 200 LFM airflow directed across the circuit.

Maximum transistor temperature in still air (0 LFM) and with 200 LFM air flow for the buck converters in figure 6

The corresponding conversion efficiency for both converters, operating with zero airflow, is plotted in figure 8.

Efficiency comparison between the MOSFET and eGaN FET-based buck converters in figure 6 with no airflow

There is an improvement of over 3 percentage points in peak efficiency (25% reduction in losses) with eGaN FETs in the circuit.

Summary

Chipscale packaging is more efficient than conventional power transistor packaging. In addition to having lower parasitic resistance and inductance, it has a smaller footprint and improved thermal efficiency. Add to these attributes the superior electrical performance of GaN-on-silicon power transistors and it is clear that the aging power MOSFET is falling further and further behind.

References
[1] Efficient Power Conversion EPC2021 datasheet, www.epc-co.com
[2] Efficient Power Conversion EPC2001 datasheet, www.epc-co.com
[3] A. Lidow, J. Strydom, M. de Rooij, D. Reusch, “GaN Transistors for Efficient Power Conversion,” Second Edition, Wiley, ISBN 978-1-118-84476-2, pages 76-83.
[4] Infineon Blade BSN012N03LS datasheet, www.infineon.com
[5] Infineon CanPAK S-size BSF134N10NJ3 G datasheet, www.infineon.com
[6] Infineon CanPAK M-size BSB012N03LX3 G datasheet, www.infineon.com
[7] Infineon S3O8 BSZ075N08NS5 datasheet, www.infineon.com
[8] Texas Instruments S308 Dual Cool SON 3.3x3.3mm CSD16323Q3C datasheet, www.TI.com
[9] Infineon Super SO8 BSC010N04LS datasheet, www.infineon.com
[10] Texas Instruments Super SO8 Dual Cool SON 5x6mm CSD16321Q5C datasheet, www.TI.com
[11] D. Reusch, D. Gilham, Y. Su and F.C. Lee, “Gallium nitride based multi-megahertz high density 3D point of load module,” APEC 2012. pp.38-45. Feb. 2012.

 

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