Time Controlled Power-Save Mode

Posted on 01 December 2019

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More Flexibility For Low-Power Synchronous Buck Converters

Modern synchronous buck converters for portable applications provide so called power-save mode operation to maintain high efficiency over the entire load range. At light loads, the converter operates with pulse frequency modulation (PFM mode) and provides automatic transition into pulse width modulation (PWM mode) at medium to heavy loads.

By Markus Matzberger, Portable Power Systems Engineer, Texas Instruments

 

This article discusses the basics of buck converters, the differences between PWM Mode and PFM Mode operation and describes in more detail a time controlled PFM mode technique, which is used in modern buck converters.

In several applications (e.g. audio), the PFM output ripple voltage, frequency and transitioning point between PFM and PWM operation is often a concern. With a time controlled PFM Mode, the performance can be fine tuned with external components to meet these specific application requirements.

Buck Converter Basics

Figure 1 shows a simplified schematic of a buck regulator featuring the high-side PMOS switch (Q1) and low-side NMOS rectifier (Q2). Each MOSFET also includes a back-gate diode as shown in the diagram.

Simplified Synchronous Buck Converter

A buck converter operates by applying a fixed frequency pulse width modulated (PWM) waveform to a low-pass filter composed of an inductor L and an output capacitor COUT. The filter then averages the PWM waveform, resulting in a DC output voltage. For highest efficiency considerations, low voltage DC/DC converters generally use synchronous rectification (SR) schemes for minimizing the conduction loss, refer to Figure 1.

Equation 1

To begin a discussion of DC/DC converters, a few fundamental relationships need understanding. In an ideal (lossless) buck converter, the input voltage and the duty cycle of the switch determine the output voltage.

Where the duty cycle is defined as the ratio of the main switch Q1 ON time to the switching period. This relationship holds as long as there is continuous current flowing in the inductor.

The next step is to follow the operation of the circuit for one switching cycle.

In a first step, the PWM signal turns on the main switch (Q1) and the inductor current transitions from the SR (Q2) to the switch (Q1). The current flows from the input capacitor via the high-side switch (Q1) through the inductor into the output capacitor and into the load. To close this loop, the current returns back to the input capacitor. During this phase, the current in the high-side switch (Q1) and the inductor ramps-up until the high side switch is turned off.

In a second step, the PWM signal turns off the main switch (Q1) and the inductor current transitions from the switch (Q1) to the SR (Q2). The current still flows from the inductor into the output capacitor and into the load, but it returns back through the low-side MOSFET rectifier (Q2). The inductor and rectifier current will ramp down. During the rectification cycle, the input capacitor is charged-up.

Figure 2 shows a scope plot of a buck converter operating with a load current of 200mA. The load current is equal to the average inductor current. Note that the input voltage is 3.6V and the output voltage 1.8V, therefore the duty cycle is c.a. 50%.

Buck Converter, Fixed Frequency PWM Operation

Another important relationship relates the inductor value to the amount of AC ripple current in the converter.

Equation 2

The inductor peak current is defined as:

Equation 3

Conversely, the inductor valley current is defined as:

Equation 4

Why PFM Mode?

The formulation “PFM mode” stands for Pulse Frequency Modulation. PFM is a nonlinear operation in which a series of inductor current pulses are applied to the load and output capacitor to maintain the output voltage within preset boundaries. This mode effectively lowers the frequency of the switching-cycle events, thereby lowering the switching losses in the converter.

In modern low-power DC/DC regulators, when Power Save Mode (PSM) operation is enabled converters are automatically turning into PFM mode regulation under light load condition.

During PFM operation, the Switched Mode Power Supply (SMPS) is kind of in sleep mode. Only the internal reference and a low quiescent current comparator are enabled to supervise the output voltage, a nonlinear control scheme is applied.

Most of the other functions of the DC/DC converter are turned-off, thereby dramatically reducing the quiescent current consumption down to c.a. 15 to 20uA. Once the output voltage falls below a certain threshold, the DC/DC converter wakes up and operates until the output voltage is within its regulation limits.

PFM operation is primarily aimed to increase the DC/DC converter’s efficiency under light load conditions. But as a side effect, it has influence on two major parameters of the DC/DC converter:
- output voltage ripple
- switching / burst frequency

 The increase in conversion efficiency at light loads can be seen in Figure 3.

Efficiency Comparison - PFM Mode vs. Fixed PWM Mode

Figure 4 shows the change in PFM switching frequency and its impact on the output ripple voltage as the output current is increased from 1.5mA to 50mA. This example is based on the TPS62260 device (2.25MHz, 600mA buck regulator) showing constant PFM output ripple voltage, whilst the switching frequency is increasing with higher load conditions.

PFM Mode Frequency vs. Load Current (TPS6226x)

Time Controlled PFM Mode ( TPS62240, TPS62260, TPS62290 )

The TPS62240, TPS62260, TPS62290 family of 2.25MHz buck converters features a single threshold, variable on-time controlled PFM mode. These devices feature an on-time controlled inductor peak current modulation (vs. fixed inductor peak current) when operating with a VOUT/VINratio of less than 85%.

In this case, the inductor peak current depends on the effective inductance value. As a result, the output ripple voltage and the PFM frequency can be influenced by both, the inductor and output capacitance.

On-Time Controlled PFM Scheme (TPS62240, ‘260, ‘290)

Below equation helps to estimate the PFM inductor peak current. The time period (T1) reflects the nominal duration of a single PFM pulse.

Equation 5

With T1 ≈ 0.62μs, L in μH

In PFM mode, the device typically operates in a single pulse mode and reduces progressively the dead-time between pulses as the load current increases. As a matter of facts, the PFM frequency increases up to the point it can not be supported any longer by a single pulse. To maintain the output voltage within regulation, the device adds further pulses to the sequence of maximum 16 pulses. In case the load requirement can no longer be supported by a series of 16 pulses, the device will automatically enter PWM mode operation.

Single Threshold PFM Regulator Block Diagram

The load current at which the device transitions from PFM into PWM mode is mainly a function of the input and output voltages as well as the inductance value.

Equation 6

A typical application circuit for 1.8V output voltage using TPS62240 is given in Figure 7. The characteristics in Figure 8 to Figure 10 have been measured with this circuit.

Typical Application Circuit of TPS62240 for 1.8V Output Voltage

Figure 8 shows the difference in the output ripple voltage that can be achieved by using different inductance. In the left graph, a 2.2μH inductor has been connected to the device resulting in a 20mV peak to peak ripple voltage at 10mA load. In the right hand-side graph, the inductor value is roughly double, the output ripple voltage half and the PFM frequency is approx. twice as high. In both cases an effective capacitance of 6μF (i.e. 10μF nominal) has been used.

Output Ripple Voltage vs. Various Inductors

Figure 9 shows different PFM frequency characteristics over load current and LC filter combinations. The PFM/PWM mode transition point is primarily defined by the inductor value and the operating condition and nearly independent of the output capacitor value.

PFM frequency vs. load current vs. LC components

The PFM/PWM transition point can be tailored by the inductor selection. For audio and low-power RF transmitter applications, an earlier PFM/PWM transition point (i.e. at low load current) can help to minimize interferences with other noise sensitive components in these systems. The fixed frequency operation in PWM mode provides the lowest output ripple.

The PFM frequency characteristic starts at a few kHz (at very light load) and increases with rising load current. Further load increase increments the PFM pulse count, thus lowers the PFM burst frequency down to the PFM/PWM transition point. The PFM frequency at this point can be approximated as:

Equation 7

Figure 10 presents the peak-to-peak output ripple voltage characteristic vs. load current for a set of inductor and output capacitor combinations.

PFM output ripple voltage vs. load currents vs. LC components

For a given output capacitor (e.g. 10uF 6.3V 0603, 6uF effective), the output ripple voltage characteristic can be improved with larger inductances (e.g. 2.2μH to 3.3μH). Furthermore, the PFM/PWM mode transition point is shifted towards lower output current values.

For a given inductor (e.g. 2.2μH), increasing the effective output capacitance (2x 10uF 6.3V 0603, 12uF effective) helps to improve the output ripple voltage performance without impacting the PFM/PWM transition point. Suitable inductor ranges from 2.2μH to 4.7μH, output capacitors from 10μF to 22μF.

Conclusion

In practice, some designers of portable systems try to avoid designs with variable-frequency converters because of the concern about EMI or other aspects related to variable-frequency operation. In some cases, these concerns are valid due to the interaction of PFM converters with sensitive subsystems elsewhere in the portable product. However, PFM architecture offers real benefits.

The basic operational differences between PWM and PFM architectures have been reviewed. TI continuously drives forward the development and optimization of PFM techniques to achieve best performance on key parameters such as output ripple voltage and quiescent current.

If it is determined that the variable frequency operating range is too wide for a sensitive application, the system designer should consider the use of time controlled PFM mode. This offers some more flexibility to adjust the PFM output ripple voltage, to tune the burst frequency characteristic and certainly offers better efficiency over fixed-frequency PWM mode.

As with many engineering problems, there is no single best answer but a range of application specific issues that need to be considered.

 

 

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