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Posted on 11 March 2019

# WPC Standard Wireless Charger Receiver Solution Based on FPGA

By Louis Tang, Fairchild Semiconductor

### Background

With the vigorous development of wireless charger technology, and as more smartphone users are plagued by various charging cables, the convenience of a wireless charger will be widely accepted and adopted. Currently there are three different wireless charger standards – WPC (Qi), PMA and A4WP. The WPC Qi standard is more popular for use in smartphone applications. Now, many smartphone OEMs have launched wireless charger solutions which support the WPC standard. This paper will focus on the WPC standard’s wireless charger receiver system and how it relates to the detailed system architecture based on the FPGA.

### WPC Standard Overview

WPC Qi standard provides a detailed description of the wireless charger system, including the communication and transport protocols. Power transfer always takes place from a base station to a mobile device. A base station contains a subsystem—referred to as a power transmitter—that comprises a primary coil, and a mobile device contains a subsystem—referred to as a power receiver—that comprises a secondary coil.

Figure 1: Basic system configuration

Figure 1 illustrates the basic system configuration. As shown, a power transmitter comprises two main functional units, namely a power conversion unit and a communications and control unit. The control and communications unit regulates the transferred power to the level that the power receiver requests. A power receiver comprises a power pick-up unit and a communications and control unit.

The power receiver is at the side of the mobile phone, so the following will mainly introduce the power receiver system, and give the wireless charger receiver solution based on FPGA.

### Power Receiver System Based on FPGA Overview

According to the WPC Qi standard, the power receiver system will contain a power pick-up unit and a communication and control unit. Examples will provide a detailed receiver solution that fully meets the WPC Qi standard’s requirements. Figure 2 shows the architecture of the power receiver system based on a FPGA.

Figure 2: System architecture

As shown in Figure 2, the receiver system contains two subsystems, one is the analog module and another is the digital module. The analog module is composed of discrete components, which includes the full-bridge rectifier module, V/I sense and AD control module, communication module and DC-DC module. The digital module is built into the FPGA, using the Verilog language to write the programs. The digital core module can be divided into three main sub-modules: first is the communication and PWM control module, second is the calculate module, and third is the Rx and Tx (receiver and transmitter) module. These modules are described in more detail below.

### Analog Module

The secondary coil is the power source of the analog part; the primary coil and secondary coil form the two halves of a coreless resonant transformer. Through electromagnetic coupling, the alternating magnetic field will generate the AC power at the secondary coil, and then the full-bridge rectifier will convert AC to DC. Figure 3 shows some of the analog module’s schematic.

### Full-bridge Rectifier

In this solution, the FAN156 (U10) comparator, the FDMA8878 (M1, M2, M3, M4) N-channel MOSFET and the FAN7085 and FAN3180 (U2, U3, U4, U5) MOSFET drivers comprise the full-bridge rectifier. The FAN156 device’s output signal feeds directly into the FPGA, and then the FPGA will give the control signal H1, L1, H2 and L2 to the full-bridge rectifier.

The FAN156 comparator is used to detect the polarities on the ends of the coil.

Figure 3: Part of the anolog module's schematic

As shown in the schematic, if coil + is positive and coil - is negative, then the FAN156 comparator will give a “H” signal to FPGA. In a similar way, if coil + is negative and coil - is positive, then the FAN156 comparator will give a “L” signal to FPGA. The PWM control module will then give its output based on these inputs. From the fullbridge rectifier perspective, if coil + is positive and coil - is negative, then the N-channel MOSFET (M1 and M4) should turn-on and (M2 and M3) should turn-off. Similarly, if coil + is negative and coil - is positive, then the N-channel MOSFET (M2 and M3) should turn-on while the M1 and M4 should turn-off. These form a rectification cycle and there should be dead-time between the M1 and M4 opening and the M2 and M3 closing, or M2 and M3 opening and M1 and M4 closing. This is because there is a potential risk, for example, when the FPGA sends the instruction to let M1 and M4 turn-on, at the same time, M2 and M3 is on and is going to turn-off, so the M1 and M2 will form a low-impedance path. This kind of situation should be avoided. There needs to be dead-time to ensure M2 is turned-off before M1 is turned-on. In this solution, the dead-time can be added in the FPGA PWM control module. Figure 4 illustrates the timing diagram of the PWM control module. Please note that “1” means logic “H”, “0” means logic “L”, and FAN7085 is negative logic.

Figure 4: PWM control module timing diagram

### V/I Sense and AD Control Module

V/I sense and AD module is in charge of voltage and current data acquisition, these parameters are very important for the FPGA control module. In this solution, 10-bit ADC (U8, U9), differential amplifier (U6) and FAN4931 device (U7) comprise the V/I sense and AD control module. Use a 20 milliohm precise resistor to sense the current, and the differential amplifier will amplify the voltage drop across the precise resistor. For example, set the differential amplifier with a 100V/V gain, and the reference voltage of the ADC is 2.5V, so the maximum current that can be detected is 1.25A, and the theoretical accuracy is less than 2mA.

The precise divider resistors R9 and R10 are used to sense the rectified DC voltage Vrec, if R9=75K and R10=24.9K as show in the schematic, because the ADC’s reference voltage is 2.5V, so the maximum detectable voltage is 10V, and the theoretical accuracy is less than 10mV. The FAN4931 device is used as a voltage follower, and to achieve the impedance matching between the ADC and divider resistors.

The control signal of the ADC, /CS and CLK, comes from the FPGA control module. Their output data will feed into the FPGA, the calculate module will use this data to calculate the received power, and the control module will use this data as the verilog program’s sensitive signal.

### Digital Module

The digital core module is built into the FPGA and it is crucial for the power receiver system. Communication and PWM Control Module The WPC Qi standard provides a detailed description of the power transfer phases, from a system control perspective. Power transfer from a power transmitter to a power receiver comprises four phases – start (selection), ping, ID & C (identification and configuration), and PT (power transfer). Figure 5 illustrates the relationship between the phases.

Figure 5: Power transfer stages

Every time the receiver board is placed on the wireless charger pad, the control programs will enter a state 0. If the connection (ping) is successful, the receiver will go into charging status. Thus the control program will stay on the state 5 and 6, the control module will send out a control error packet to adjust the charging current, and will also send the received power packet to implement the FOD (Foreign Object Detection) function.

Figure 6: Control module state machine

Calculate and Rx and Tx Module The calculate module is used to calculate the signal strength, control error and the receive power. In the analog module, the ADC will give the voltage and current information to the FPGA, and the calculate module will get the signal strength, control error and received power, and send it to the Rx and Tx module.

The Signal Strength value can be calculated with the formula below:

Where U is the monitored variable, and Umax is the maximum value, which the power receiver expects for that variable during a digital ping. Note that the power receiver shall set the signal strength value to 255 in the case that U = Umax. Here use the rectified voltage Vrec as the U, the ADC will give the 10-bit digitized voltage to the FPGA, and the FPGA will use it to calculate the Signal Strength.

The Received Power value is calculated as shown below:

Where if the Received Power Value is 128, that means the Received Power is 5W.

The Rx and Tx module use the data which comes from the calculate module to process the packets, and send these packets to the power transmitter. The WPC Qi standard defines the data format in the communication. In every data transmission, one packet will be transferred. One data packet is formed by a preamble (>11 bit one) for bit synchronization, one byte message head which indicates the packet type, the message information (1..27 byte) and one checksum byte. One data byte is an 11-bit serial format. This format consists of one bit start bit, the eight data bits, one parity bit and one bit stop bit. The start bit is a ZERO. The order of data bits is least significant bit (LSB) first. The parity bit is odd and the stop bit is a ONE. Data bit is encoded in differential bi-phase code and its speed is 2Kbps. The data format is shown in Figure 7.

Figure 7: Data format

Conclusion Through testing and analyzing, the demo board works well on the major OEM ’s wireless charger pad. This shows that the system is stable and reliable, which has some practical values. Figure 8 shows this solution being used to charge a handset on a major OEM’s wireless charger pad.

Figure 8: Wireless charging on the wireless charging pad

As portable devices increase in popularity, convenient charging is going to be the growing trend, and wireless charging may be the best choice. This solution adopts a few discrete devices and one FPGA, to verify the design of the Qi standard charger receiver, and has the very high technical reference value to the wireless charger receiver system’s architecture and design. With the wireless charger market developing, this method can be very easily integrated into new silicon.

Reference
[1] “System Description Wireless Power Transfer Volume I: Low Power, Part 1: Interface Definition V1.1.1 July 2019”, Wireless Power Consortium.

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## One Response

1. xhl says:

Hello,I'm a student majoring in integrated circuit engineering，and this article is useful for my postgraduate research,can you please provide this design's verilog or VHDL code to me,and if you can provide any other material or document about wireless charging and it's digital control based on FPGA,I will thank you very much.My E-mail is 774930344@qq.com and thank you anyway.

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